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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Piia Simonen, Tampere University of Technology
Ilkka Saastamoinen, Tampere University of Technology
Mika Kuulusa, Tampere University of Technology
Jari Nurmi, Tampere University of Technology
On-chip memories can consume multiple times the area of a processor core, thus affecting to the chip costs dramatically. In this paper, three approaches for reducing program memory footprint in a DSP processor are analyzed: fully 16-bit and two versions of mixed 16/32-bit instruction encodings. A separate decompression logic is implemented between memory and core, so the 32-bit processor core is remained unchanged. Compared to the original 32-bit instruction set, the fully 16-bit ISA (Instruction Set Architecture) eliminates 22% of the program memory footprint with a 1.55 times the original runtime. Mixed 16/32-bit ISAs achieve virtually same memory size, but with a faster runtime of 1.29 times the original at best.
Index Terms:
instruction memory, memory compression, DSP processor, ISA
Citation:
Piia Simonen, Ilkka Saastamoinen, Mika Kuulusa, Jari Nurmi, "Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor," delta, pp.477, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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