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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Flexible Embedded SRAM Compiler
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Yong Liu, Tsinghua University
Zhiqiang Gao, Tsinghua University
Xiangqing He, Tsinghua University
SRAM Compiler uses predefined building blocks or leaf cells and connectivity information to compile SRAMs of user-specified size. In this paper, a high-speed embedded SRAM Compiler is described. It is based on TSMC's 0.5 ?m CMOS process. It can compile both single-port and dual-port SRAMs. SRAM is a completely synchronous architecture with a maximal capacity 16k* 64=1Mb bits. The compiler generates the layout, behavioral level models, schematic symbols, and a layout abstraction to place and route. The program in Skill language can automatically complete the creation of all the models in different levels. The SRAM Compiler has a friendly user interface. Users can specify the necessary parameters and then get all the results. The SRAM Compiler can be easily integrated into Cadence and other CAD frameworks.
Citation:
Yong Liu, Zhiqiang Gao, Xiangqing He, "A Flexible Embedded SRAM Compiler," delta, pp.474, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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