CSDL Home D DELTA 2002 Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
Yong Liu , Tsinghua University
Zhiqiang Gao , Tsinghua University
Xiangqing He , Tsinghua University
SRAM Compiler uses predefined building blocks or leaf cells and connectivity information to compile SRAMs of user-specified size. In this paper, a high-speed embedded SRAM Compiler is described. It is based on TSMC's 0.5 ?m CMOS process. It can compile both single-port and dual-port SRAMs. SRAM is a completely synchronous architecture with a maximal capacity 16k* 64=1Mb bits. The compiler generates the layout, behavioral level models, schematic symbols, and a layout abstraction to place and route. The program in Skill language can automatically complete the creation of all the models in different levels. The SRAM Compiler has a friendly user interface. Users can specify the necessary parameters and then get all the results. The SRAM Compiler can be easily integrated into Cadence and other CAD frameworks.
Yong Liu, Zhiqiang Gao, Xiangqing He, "A Flexible Embedded SRAM Compiler", DELTA, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002 2002, pp. 474, doi:10.1109/DELTA.2002.994676