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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Test Power: a Big Issue in Large SOC Designs
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Y. Bonhomme, Universit? Montpellier II
P. Girard, Universit? Montpellier II
C. Landrault, Universit? Montpellier II
S. Pravossoudovitch, Universit? Montpellier II
Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this work, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.
Index Terms:
Low Power Testing, Test Power, BIST, Scan, DfT
Citation:
Y. Bonhomme, P. Girard, C. Landrault, S. Pravossoudovitch, "Test Power: a Big Issue in Large SOC Designs," delta, pp.447, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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