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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Yoshinobu Higami, Ehime University
Shin-ya Kobayashi, Ehime University
Yuzo Takamatsu, Ehime University
This paper presents a method to modify test vectors for reducing power dissipation in CMOS sequential circuits. Test vectors are modified by inverting values of primary inputs one by one. With respect to the reduction of power dissipation, we check if the average number of signal transition gates is decreased and if the maximum number of signal transition gates is not increased. Original fault coverage is guaranteed by logic simulation and fault simulation. The effectiveness of the proposed method is shown by experimental results for ISCAS'89 benchmark circuits.
Index Terms:
CMOS circuit, Power dissipation, Test generation, Fault simulation
Citation:
Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, "Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits," delta, pp.431, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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