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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
IDDT Test Methodologies for Very Deep Sub-micron CMOS Circuits
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Ali Chehab, Multilink Technology Corporation
Rafic Makki, University of North Carolina at Charlotte
Michael Spica, Intel Corp.
David Wu, Intel Corp.
In this paper, we investigate three iDDT-based test methodologies, Double Threshold iDDT, Delta iDDT, and Delayed iDDT, and we compare their effectiveness in the detection of defects in very deep sub-micron random logic circuits. The target defects are resistive opens and resistive bridges. We present preliminary simulation results of 49 defects to study the defect sensitivity of each of the three test methods. This paper reports our preliminary results on these three test methods using a relatively small transistor-level sample circuit, and is not intended to imply any feasibility in a production environment. The test methods presented herein are the subject of a current invention disclosure.
Citation:
Ali Chehab, Rafic Makki, Michael Spica, David Wu, "IDDT Test Methodologies for Very Deep Sub-micron CMOS Circuits," delta, pp.403, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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