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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Hideyuki Ichihara, Hiroshima City University
Tomoo Inoue, Hiroshima City University
Test compression/decompression scheme using statistical coding is proposed as a design-for-testability (DFT) in order to reduce test application cost. In this scheme, a given test set of a VLSI circuit is compressed by statistical coding beforehand, and then it is decompressed while the VLSI circuit is tested. Previously, we proposed a method for generating test sets suitable to the test compression scheme. The method generates a small compressed test set, although the number of test-patterns included in the test set is not always small. In this paper, we propose a method to generate highly compressible test sets while keeping the number of generated test sets small. Experimental results show that our method can generate small and compressible test sets in small computational time.
Index Terms:
test compression, statistical code, test generation, test compaction, ATE
Citation:
Hideyuki Ichihara, Tomoo Inoue, "Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding," delta, pp.396, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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