This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Path-Oriented Test Data Generation of Behavioral VHDL Description
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Christophe Paoli, University of Corsica
Marie-Laure Nivet, University of Corsica
Jean-François Santucci, University of Corsica
Antoine Campana, University of Corsica
The validation of HDL descriptions before their synthesis is one of the principal problems related to the top-down design process of complex circuits. This task can be accomplished according two approaches: formal verification or simulation based validation. Because formal verification, in spite of recent progress, is only feasible for small descriptions, simulation is still the best way to test hardware design. One of the main problem of such approach is to generate test vectors in order to verify design specifications. We think that high level HDL description represents a new source of information about the circuit which may be useful in test data generation field. The approach presented in this paper borrows techniques used successfully in software testing area for test vectors generation. This paper focus on a path-oriented test data generator.
Index Terms:
VHDL, High level design validation, simulation-based validation, software testing techniques, constraint logic programming language
Citation:
Christophe Paoli, Marie-Laure Nivet, Jean-François Santucci, Antoine Campana, "Path-Oriented Test Data Generation of Behavioral VHDL Description," delta, pp.382, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
Usage of this product signifies your acceptance of the Terms of Use.