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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
M. Renovell, LIRMM - UM2
P. Faure, LIRMM - UM2
P. Prinetto, Polytecnico de Torino
Y. Zorian, Logic Vision Inc.
This paper proposes a new and original solution to test the uni-dimensionnal interconnect architecture of a RAM based FPGA by exploring the specific properties of these blocks. The method to find a reduced set of configurations is proposed and the sequence of test vectors required for each configuration is given.
Index Terms:
FPGA, Test
Citation:
M. Renovell, P. Faure, P. Prinetto, Y. Zorian, "Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA," delta, pp.297, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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