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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
On-line Diagnosis and Reconfiguration of FPGA Systems
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Anna Antola, Politecnico di Milano
Mariagiovanna Sami, Politecnico di Milano
Vincenzo Piuri, University of Milan
Fault tolerance is becoming an important issue for the effective use of FPGA-based architectures in mission-critical applications. This paper introduces an innovative approach to design FPGA systems with on-line diagnosis and reconfiguration, at a limited cost in terms of FPGA redundant resources and interconnections. The technique is based on high-level synthesis of the self-checking datapath to be mapped on the FPGA. The analysis of the computation flow allows for locating the necessary checking points. Scheduling is performed so as to minimize the circuit complexity, while satisfying the maximum latency allowed by the application. Allocation is performed as a suited trade-off between the circuit complexity and the reconfiguration efficiency. Problems and constraints due to re-use of units in different points of the computation are taken into account. The faulty block replacement policy will be discussed, together with its implication in terms of re-use and of interconnection re-routing.
Index Terms:
FPGA, fault tolerance, on-line detection, reconfiguration, diagnosis
Citation:
Anna Antola, Mariagiovanna Sami, Vincenzo Piuri, "On-line Diagnosis and Reconfiguration of FPGA Systems," delta, pp.291, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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