CSDL Home D DELTA 2002 Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
Joerg Vollrath , Infineon Technologies
The sense amplifier design and the bit line architecture determine the signal limit for a dynamic memory cell readout. Increasing memory sizes, smaller feature sizes and lower operating voltages make it more important to understand the cell signal sensing operation, the signal of memory cells and the limiting factors. This paper presents a measurement method to evaluate the signal created by the memory cell and the sense amplifier uniformity at product level. Measurements of the sense amplifier offset distribution and sense amplifier signals for "0"s and '1's for all memory cells will be presented. Spatial analysis gives further insight into the sensing limitations. The results for a 64Mbit 0.19um memory device will be shown, which highlighted a sense amplifier imbalance. The results can be implemented as circuit models for electrical simulations.
Test, DRAM, Signal margin, Diagnosis, Memory
Joerg Vollrath, "Signal Margin Analysis for Memory Sense Amplifiers", DELTA, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002 2002, pp. 123, doi:10.1109/DELTA.2002.994600