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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Interconnect IP Node for Future System-on-Chip Designs
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
I. Saastamoinen, Tampere University of Technology
D. Sigüenza-Tortosa, Tampere University of Technology
J. Nurmi, Tampere University of Technology
In this paper an interconnect IP (Intellectual Property) node architecture for flexible on-chip communication is introduced. This architecture is targeted for communication in future gigatransistor SoC (System-on-Chip) designs. The interconnect IP will be used as a testing platform when the efficiency of network topologies and routing schemes are investigated for on-chip environment. The interconnect node uses packet based communication and forms a reusable component itself. The node is constructed from a collection of parameterized and reusable hardware blocks. Those blocks include components such as FIFO buffers, routing controllers and standardized interface wrappers. A node can be tuned to fulfill the desired characteristics of communication by selecting the internal architecture of the node properly. In the future the IP node forms a basic building component in SoC implementations.
Index Terms:
System-on-Chip, on-chip communication, packet network, reuse
Citation:
I. Saastamoinen, D. Sigüenza-Tortosa, J. Nurmi, "Interconnect IP Node for Future System-on-Chip Designs," delta, pp.116, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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