This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Novel CAM/RAM Based Buffer Manager for Next Generation IP Routers
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Chie Dou, National Yunlin University of Science and Technology
Shing-Jeh Jiang, Computer & Communications Research Laboratories
Kuo-Cheng Leu, Computer & Communications Research Laboratories
This paper proposes an integrated CAM/RAM based buffer manager for next-generation IP routers. Buffer allocation is accomplished by inspecting the length field in the IP header of an incoming packet, the wasted buffer area is optimized, and the hardware implementation is simple. The data buffer is configured according to the cumulative packet size distribution observed from the underlying network thus increases the efficiency of the memory utilization. The buffer manager also supports the multicast management in an elaborate manner. In addition, it supports different-sized block movement of the packet data between the data buffer and the transmission media. Finally, it need not have to maintain the free buffer list, i.e., enormous and repeated 'insert' and 'delete' operations of pointers in a linked list are eliminated.
Index Terms:
buffer manager, content addressable memory, IP router, CAM/RAM integration
Citation:
Chie Dou, Shing-Jeh Jiang, Kuo-Cheng Leu, "A Novel CAM/RAM Based Buffer Manager for Next Generation IP Routers," delta, pp.111, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
Usage of this product signifies your acceptance of the Terms of Use.