CSDL Home D DELTA 2002 Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
Zhenghui Lin , Shanghai Jiao Tong University
Haifeng Zhou , Shanghai Jiao Tong University
In this paper, we present a prototype of VHDL RTL synthesis system- VHB. This prototype can be divided into three parts. The first part is a VHDL synthesis subset parser, the second part is an optimizer at language level, and the third part is an inferencer responsible for getting the netlist. The parser checks whether the input VHDL descriptions are in accordance with the grammar of synthesis subset, and generates the parsing tree of input descriptions. The parsing tree generated by the parser is provided to the second part of the prototype to perform language level optimization, which includes redundant and ambiguous elimination in assignment statements; expression optimization; common sub-expression extraction; operator reordering; resource sharing and loop unrolling. The task of the third part is very simple, which generates the netlist.
VHDL RTL synthesis, formal semantics, parser, ambiguous grammar, language level optimization, inference
Zhenghui Lin, Haifeng Zhou, "Research on VHDL RTL Synthesis System", DELTA, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002 2002, pp. 99, doi:10.1109/DELTA.2002.994596