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Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
ISBN: 0-7695-1453-7
pp: 86
Raimund Ubar , Tallinn Technical University
Jaan Raik , Tallinn Technical University
Eero Ivask , Tallinn Technical University
Marina Brik , Tallinn Technical University
ABSTRACT
A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. DDs are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows to reduce time expenses Compared to the traditional gate-level fault simulation approach
INDEX TERMS
Digital systems, register transfer and gate level descriptions, fault simulation, decision diagrams
CITATION
Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik, "Multi-Level Fault Simulation of Digital Systems on Decision Diagrams", DELTA, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002 2002, pp. 86, doi:10.1109/DELTA.2002.994594
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