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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Multi-Level Fault Simulation of Digital Systems on Decision Diagrams
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Raimund Ubar, Tallinn Technical University
Jaan Raik, Tallinn Technical University
Eero Ivask, Tallinn Technical University
Marina Brik, Tallinn Technical University
A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. DDs are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows to reduce time expenses Compared to the traditional gate-level fault simulation approach
Index Terms:
Digital systems, register transfer and gate level descriptions, fault simulation, decision diagrams
Citation:
Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik, "Multi-Level Fault Simulation of Digital Systems on Decision Diagrams," delta, pp.86, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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