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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Constrained Specification-Based Test Stimulus Generation for Analog Circuits Using Nonlinear Performance Prediction Models
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
Soumendu Bhattacharya, Georgia Institute of Technology
Abhijit Chatterjee, Georgia Institute of Technology
The problem of signature-based testing of analog circuits has received a lot of attention in the recent past. In signature-test, a carefully optimized stimulus is applied to the CUT and its specifications are predicted from the test response. This results in test time reduction by 10X-50X. In this paper, a new test generation approach is presented for optimizing a test stimulus that increases the accuracy of specification prediction from the test response. Nonlinear models are used to map the test response to the circuit's specifications. They are accurate in the regions of the measurement space where the circuit's specifications are the most sensitive to process perturbations and maximum information about the CUT's specifications is contained in the observed test response. The test stimulus can be constrained to lie within a specified bandwidth or a specified voltage or current range. This ability is further used to generate wafer-probe and assembled-package tests.
Index Terms:
Wafer-probe Test, Assembled Package Test, Multivariate Adaptive Regression Splines, Genetic Algorithm
Citation:
Soumendu Bhattacharya, Abhijit Chatterjee, "Constrained Specification-Based Test Stimulus Generation for Analog Circuits Using Nonlinear Performance Prediction Models," delta, pp.25, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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