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13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
A synthesis method to propagate false path information from RTL to gate level
Vienna, Austria
April 14-April 16
ISBN: 978-1-4244-6612-2
| ASCII Text | x | ||
| Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara, "A synthesis method to propagate false path information from RTL to gate level," 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 197-200, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/DDECS.2010.5491787, author = {Satoshi Ohtake and Hiroshi Iwata and Hideo Fujiwara}, title = {A synthesis method to propagate false path information from RTL to gate level}, journal ={13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems}, volume = {0}, year = {2010}, isbn = {978-1-4244-6612-2}, pages = {197-200}, doi = {http://doi.ieeecomputersociety.org/10.1109/DDECS.2010.5491787}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems TI - A synthesis method to propagate false path information from RTL to gate level SN - 978-1-4244-6612-2 SP197 EP200 A1 - Satoshi Ohtake, A1 - Hiroshi Iwata, A1 - Hideo Fujiwara, PY - 2010 VL - 0 JA - 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems ER - | |||
This paper proposes a new synthesis method for propagating information of paths from register transfer level (RTL) to gate level. The method enables false path identification at RTL without not only enforcing strong constraints on logic synthesis but also loss of the information about false paths identified. Experiments show that the proposed method can reduce hardware and timing overhead and improve propagability of false path information through logic synthesis compared with the previous methods.
Citation:
Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara, "A synthesis method to propagate false path information from RTL to gate level," ddecs, pp.197-200, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
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