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13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop
Vienna, Austria
April 14-April 16
ISBN: 978-1-4244-6612-2
ASCII Text
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Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang, "A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop," 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 285-288, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010.
 
 
BibTex
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@article{ 10.1109/DDECS.2010.5491766,
author = {Kuo-Hsing Cheng and Chang-Chien Hu and Jen-Chieh Liu and Hong-Yi Huang},
title = {A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop},
journal ={13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems},
volume = {0},
year = {2010},
isbn = {978-1-4244-6612-2},
pages = {285-288},
doi = {http://doi.ieeecomputersociety.org/10.1109/DDECS.2010.5491766},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
TI - A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop
SN - 978-1-4244-6612-2
SP285
EP288
A1 - Kuo-Hsing Cheng,
A1 - Chang-Chien Hu,
A1 - Jen-Chieh Liu,
A1 - Hong-Yi Huang,
PY - 2010
VL - 0
JA - 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
ER -
 
Kuo-Hsing Cheng, Department of Electrical Engineering, National Central University, Taiwan
Chang-Chien Hu, Department of Electrical Engineering, National Central University, Taiwan
Jen-Chieh Liu, Department of Electrical Engineering, National Central University, Taiwan
Hong-Yi Huang, Graduate Institute of Electrical Engineering, National Taipei University, Taiwan
This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.
Citation:
Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang, "A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop," ddecs, pp.285-288, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
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