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13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks
Vienna, Austria
April 14-April 16
ISBN: 978-1-4244-6612-2
| ASCII Text | x | ||
| Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Chatelet, "A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks," 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 305-308, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/DDECS.2010.5491763, author = {Farid Lahrach and Abderrazek Abdaoui and Abderrahim Doumar and Eric Chatelet}, title = {A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks}, journal ={13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems}, volume = {0}, year = {2010}, isbn = {978-1-4244-6612-2}, pages = {305-308}, doi = {http://doi.ieeecomputersociety.org/10.1109/DDECS.2010.5491763}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems TI - A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks SN - 978-1-4244-6612-2 SP305 EP308 A1 - Farid Lahrach, A1 - Abderrazek Abdaoui, A1 - Abderrahim Doumar, A1 - Eric Chatelet, PY - 2010 VL - 0 JA - 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems ER - | |||
In this paper we propose a novel SRAM-based FPGA architecture suited for mapping designs when defect and fault tolerance are needed. The proposed fault tolerant (FT) method employ triple modular redundancy (TMR) combined with master-slave technique (MST). Specifically, the FT-based MST technique aims to build up the SRAM-based FPGA by master-slave units (MSU). Each MSU consists of two kinds of configurable logic blocks (CLB): CLB-master (CLB-M) and CLB-slave (CLB-S). With this new architecture both, single and double faults can be tolerated when they occur in the MSU unit by using partial reconfiguration. Our proposed approach provides also accurate location of the faulty CLB-M. In this paper, we prove that the reliability of the proposed method is greater than that proposed by other previous work employing similar overhead.
Citation:
Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Chatelet, "A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks," ddecs, pp.305-308, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
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