A hybrid genetic algorithm for constrained hardware-software partitioning

Minimization of Large State Spaces using Symbolic Branching Bisimulation (Abstract)

pp. 7-12

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Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis (Abstract)

pp. 13-18

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A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology (Abstract)

pp. 19-24

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Six subthreshold full adder cells characterized in 90 nm CMOS technology (Abstract)

K. Granhaug

S. Aunet

pp. 25-30

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A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication (Abstract)

M. Gade

pp. 31-36

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Comprehensive design of a high frequency PLL synthesizer for ZigBee application (Abstract)

pp. 37-41

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A contextual resources use: a proof of concept through the APACHES' platform (Abstract)

T. Gil

pp. 42-47

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LEON-2: General Purpose Processor for a Wireless Engine (Abstract)

C. Wolf

pp. 48-51

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ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications (Abstract)

L. Sterpone

M. Violante

pp. 52-56

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Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder (Abstract)

pp. 57-62

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Parallel Memory Architecture for Arbitrary Stride Accesses (Abstract)

E. Aho

J. Vanne

T.D. Hamalainen

pp. 63-68

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Architecture Design for the Context Formatter in the H.264/AVC Encoder (Abstract)

G. Pastuszak

pp. 69-70

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Recognition of DRM signal in frequency domain and hardware demands (Abstract)

L. Ruckay

pp. 71-72

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ISA Based Functional Test Generation with Application to Self-Test of RISC Processors (Abstract)

V.V. Belkin

S.G. Sharshunov

pp. 73-74

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How to Improve a set of design validation data by using mutation-based test (Abstract)

pp. 75-76

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Design and verification methodology for reconfigurable designs in atmel FPSLIC (Abstract)

J. Kadlec

M. Danek

pp. 77-78

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Die attach quality testing by fully contact-less measurement method (Abstract)

pp. 79-80

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A flexible technique for the automatic design of approximate string matching architectures (Abstract)

T. Martinek

J. Korenek

O. Fucik

M. Lexa

pp. 81-82

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Novel Logic Circuits Controlled by Vdd (Abstract)

pp. 83-84

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Design of a Scalable Asynchronous Dataflow Processor (Abstract)

pp. 85-86

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Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits (Abstract)

null Guoyan Zhang

R. Farrell

pp. 87-88

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Test Scheduling for SOC under Power Constraints (Abstract)

J. Skarvada

pp. 89-91

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Self-refreshing Multiple Valued Memory (Abstract)

J.G. Lomsdalen

R. Jensen

Y. Berg

pp. 92-94

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Comparing Subtraction-Free and Traditional AMI (Abstract)

J. Bucek

R. Lorencz

pp. 95-97

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Dependability Computation for Fault Tolerant Reconfigurable Duplex System (Abstract)

pp. 98-100

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A New 6-bit Flash A/D Converter using Novel Two-Step Structure (Abstract)

null Shih-Chang Hsia

null Wen-Ching Lee

pp. 101-105

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A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D Converters (Abstract)

O. Subrt

P. Martinek

pp. 106-110

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Behavioral modeling of WCDMA transceiver with VHDL-AMS language (Abstract)

pp. 111-116

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A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35 um Technology (Abstract)

pp. 117-122

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Lissajous Based Mixed-Signal Testing for N-Observable Signals (Abstract)

L. Balado

E. Lupon

L. Garcia

R. Rodriguez-Montanes

J. Figueras

pp. 123-128

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PCA data preprocessing for neural network-based detection of parametric defects in analog IC (Abstract)

P. Malosek

V. Stopjakova

pp. 129-133

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Productivity and Code Quality Improvement of Mixed-Signal Test Software by applying Software Engineering Methods (Abstract)

S. Vock

U. Flogaus

H.M. von Staudt

pp. 134-138

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On the Use of Information Redundancy When Designing Secure Chips (Abstract)

R. Leveugle

V. Maingot

pp. 139-140

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PE-ICE: Parallelized Encryption and Integrity Checking Engine (Abstract)

pp. 141-142

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Normal Basis Multipliers of General Digit Width Applicable in ECC (Abstract)

M. Novotny

J. Schmidt

pp. 143-144

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Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow (Abstract)

pp. 145-146

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Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor (Abstract)

pp. 147-148

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An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem (Abstract)

pp. 149-150

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A system for transforming an ANSI C code with OpenMP directives into a SystemC description (Abstract)

pp. 151-152

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Low Level Bus Traffic Replay for the Test of Time-Triggered Communication Systems (Abstract)

E. Armengaud

pp. 153-154

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A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs (Abstract)

pp. 155-156

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Hardware/Software Based Hierarchical Self Test for SoCs (Abstract)

pp. 157-158

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Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space (Abstract)

J. Strnadel

pp. 159-160

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Design-for-Test of Asynchronous Networks-on-Chip (Abstract)

pp. 161-165

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Can Clock Faults Be Detected Through Functional Test ? (Abstract)

pp. 166-171

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A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns (Abstract)

pp. 172-177

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Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs (Abstract)

A. Krasniewski

pp. 178-183

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Fault-tolerant 2-D Mesh Network-On-Chip for MultiProcessor Systems-on-Chip (Abstract)

H. Kariniemi

J. Nurmi

pp. 184-189

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A Flexible SoPC-based Fault Injection Environment (Abstract)

pp. 190-195

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Generation and Propagation of Single Event Transients in CMOS Circuits (Abstract)

pp. 196-201

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Concurrent Testing of Digital Circuits for Advanced Fault Models (Abstract)

pp. 202-207

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Embedded Self Repair by Transistor and Gate Level Reconfiguration (Abstract)

T. Coym

pp. 208-213

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Probabilistic Testability Analysis and DFT Methods at RTL (Abstract)

pp. 214-215

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An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories (Abstract)

pp. 216-217

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Optimal Memory Address Seeds for Pattern Sensitive Faults Detection (Abstract)

S.V. Yarmolik

B. Sokol

pp. 218-219

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Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips (Abstract)

J. Jaros

V. Dvorak

pp. 220-221

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Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts (Abstract)

M. Ohlidal

J. Schwarz

pp. 222-223

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A Switch Supporting Circuit and Packet Switching for On-Chip Networks (Abstract)

pp. 224-225

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FPGA Implementation of a Fast MDCT Algorithm (Abstract)

pp. 226-227

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Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor (Abstract)

pp. 228-229

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Test Considerations about the Structured ASIC Paradigm (Abstract)

P. Bernardi

M. Grosso

pp. 230-231

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A Leakage-Based Random Bit Generator with On-line Fault Detection (Abstract)

M. Bucci

R. Luzzi

pp. 232-233

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New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal Circuits (Abstract)

V. Nagy

V. Stopjakova

pp. 234-235

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A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming (Abstract)

Z. Gajda

pp. 236-238

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SOC Diagnostic Design Using RESPIN Architecture (Abstract)

Z. Mader

M. Jarkovsky

pp. 239-241

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Dynamic Decimal Adder Circuit Design by using the Carry Lookahead (Abstract)

pp. 242-244

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Multiple Valued Counter (Abstract)

J.G. Lomsdalen

R. Jensen

Y. Berg

pp. 245-247

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HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration (Abstract)

M. Stava

O. Novak

pp. 248-250

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Sensor powering with integrated MOS compatible solar cell array (Abstract)

pp. 251-253

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March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit (Abstract)

pp. 254-259

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Minimal March-Based Fault Location Algorithm with Partial Diagnosis for All Static Faults in Random Access Memories (Abstract)

pp. 260-265

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Multiple-Vector Column-Matching BIST Design Method (Abstract)

P. Fiser

H. Kubatova

pp. 266-271

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FPGA-based fault simulator (Abstract)

L. Kafka

O. Novak

pp. 272-276

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Functional-oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage (Abstract)

pp. 277-282

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FITTest BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties (Abstract)

pp. 283-287

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