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2010 Data Compression Conference
Segment-Parallel Predictor for FPGA-Based Hardware Compressor and Decompressor of Floating-Point Data Streams to Enhance Memory I/O Bandwidth
Snowbird, Utah
March 24-March 26
ISBN: 978-0-7695-3994-2
This paper presents segment-parallel prediction for high-throughput compression and decompression of floating-point data streams on an FPGA-based LBM accelerator. In order to enhance the actual memory I/O bandwidth of the accelerator, we focus on the prediction-based compression of floating-point data streams. Although hardware implementation is essential to high-throughput compression, the feedback loop in the decompressor is a bottleneck due to sequential predictions necessary for bit reconstruction. We introduce a segment-parallel approach to the 1D polynomial predictor to achieve the required throughput for decompression. We evaluate the compression ratio of the segment-parallel cubic prediction with various encoders of prediction difference.
Index Terms:
prediction-based compresson, lossless compression, floating point, hardware, memory bandwidth
Citation:
Kentaro Sano, Kazuya Katahira, Satoru Yamamoto, "Segment-Parallel Predictor for FPGA-Based Hardware Compressor and Decompressor of Floating-Point Data Streams to Enhance Memory I/O Bandwidth," dcc, pp.416-425, 2010 Data Compression Conference, 2010
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