At-Speed Logic BIST for IP Cores

B. Cheon; X. Wen; P. Hsu; E. Lee; L.-T. Wang; S. Wu; J. Cho; H. Chao; J. Park

doi:10.1109/DATE.2005.70

D
DATE
2005
Design, Automation and Test in Europe (DATE'05) Volume 2
Abstract - At-Speed Logic BIST for IP Cores

	This Article
	PDF RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/EndNote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by B. Cheon Articles by E. Lee Articles by L.-T. Wang Articles by X. Wen Articles by P. Hsu Articles by J. Cho Articles by J. Park Articles by H. Chao Articles by S. Wu

Design, Automation and Test in Europe (DATE'05) Volume 2

At-Speed Logic BIST for IP Cores (PDF)

Munich, Germany

March 07-March 11

ISBN: 0-7695-2288-2

	ASCII Text	x
	B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, S. Wu, "At-Speed Logic BIST for IP Cores," Design, Automation & Test in Europe Conference & Exhibition, vol. 2, pp. 860-861, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005.

	BibTex	x
	@article{ 10.1109/DATE.2005.70, author = {B. Cheon and E. Lee and L.-T. Wang and X. Wen and P. Hsu and J. Cho and J. Park and H. Chao and S. Wu}, title = {At-Speed Logic BIST for IP Cores}, journal ={Design, Automation & Test in Europe Conference & Exhibition}, volume = {2}, year = {2005}, issn = {1530-1591}, pages = {860-861}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.70}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation & Test in Europe Conference & Exhibition TI - At-Speed Logic BIST for IP Cores SN - 1530-1591 SP860 EP861 A1 - B. Cheon, A1 - E. Lee, A1 - L.-T. Wang, A1 - X. Wen, A1 - P. Hsu, A1 - J. Cho, A1 - J. Park, A1 - H. Chao, A1 - S. Wu, PY - 2005 KW - null VL - 2 JA - Design, Automation & Test in Europe Conference & Exhibition ER -

B. Cheon, Samsung Electronics, Co.

E. Lee, Samsung Electronics, Co.

L.-T. Wang, SynTest Technologies, Inc.

X. Wen, Kyushu Institute of Technology

P. Hsu, SynTest Technologies, Inc., Taiwan

J. Cho, SynTest Korea, Ltd.

J. Park, SynTest Korea, Ltd.

H. Chao, SynTest Technologies, Inc., Taiwan

S. Wu, SynTest Technologies, Inc.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.70

This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.

Citation:

B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, S. Wu, "At-Speed Logic BIST for IP Cores," date, vol. 2, pp.860-861, Design, Automation and Test in Europe (DATE'05) Volume 2, 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.