Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

Takeshi Kitahara; Katsuhiro Seta; Toshiyuki Furusawa; Naoyuki Kawabe; Fimihiro Minami

doi:10.1109/DATE.2005.68

D
DATE
2005
Design, Automation and Test in Europe (DATE'05) Volume 1
Abstract - Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

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Design, Automation and Test in Europe (DATE'05) Volume 1

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction (PDF)

Munich, Germany

March 07-March 11

ISBN: 0-7695-2288-2

	ASCII Text	x
	Takeshi Kitahara, Naoyuki Kawabe, Fimihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa, "Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction," Design, Automation & Test in Europe Conference & Exhibition, vol. 1, pp. 646-647, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005.

	BibTex	x
	@article{ 10.1109/DATE.2005.68, author = {Takeshi Kitahara and Naoyuki Kawabe and Fimihiro Minami and Katsuhiro Seta and Toshiyuki Furusawa}, title = {Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction}, journal ={Design, Automation & Test in Europe Conference & Exhibition}, volume = {1}, year = {2005}, issn = {1530-1591}, pages = {646-647}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.68}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation & Test in Europe Conference & Exhibition TI - Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction SN - 1530-1591 SP646 EP647 A1 - Takeshi Kitahara, A1 - Naoyuki Kawabe, A1 - Fimihiro Minami, A1 - Katsuhiro Seta, A1 - Toshiyuki Furusawa, PY - 2005 KW - null VL - 1 JA - Design, Automation & Test in Europe Conference & Exhibition ER -

Takeshi Kitahara, TOSHIBA Corporation Semiconductor Company, Japan

Naoyuki Kawabe, TOSHIBA Corporation Semiconductor Company, Japan

Fimihiro Minami, TOSHIBA Corporation Semiconductor Company, Japan

Katsuhiro Seta, TOSHIBA Corporation Semiconductor Company, Japan

Toshiyuki Furusawa, TOSHIBA Microelectronics Corporation, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.68

This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Transfer Level) to final layout with optimizing switch transistor structure.

Citation:

Takeshi Kitahara, Naoyuki Kawabe, Fimihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa, "Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction," date, vol. 1, pp.646-647, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005

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