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Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
Sylvain Guilley, GET/Télécom Paris, CNRS LTCI
Philippe Hoogvorst, GET/Télécom Paris, CNRS LTCI
Yves Mathieu, GET/Télécom Paris, CNRS LTCI
Renaud Pacalet, GET/Télécom Paris, CNRS LTCI
Jean Provost, GET/Télécom Paris, CNRS LTCI
Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
Citation:
Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost, "CMOS Structures Suitable for Secured Hardware," date, vol. 2, pp.21414, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004
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