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Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)
A 0.18 ?m CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns (PDF)
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
| ASCII Text | x | ||
| Luis Rol?ndez, Salvador Mir, Guillaume Prenat, Ahc?ne Bounceur, "A 0.18 ?m CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns," Design, Automation & Test in Europe Conference & Exhibition, vol. 1, pp. 10706, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/DATE.2004.1268939, author = {Luis Rol?ndez and Salvador Mir and Guillaume Prenat and Ahc?ne Bounceur}, title = {A 0.18 ?m CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns}, journal ={Design, Automation & Test in Europe Conference & Exhibition}, volume = {1}, year = {2004}, issn = {1530-1591}, pages = {10706}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268939}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Design, Automation & Test in Europe Conference & Exhibition TI - A 0.18 ?m CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns SN - 1530-1591 SP EP A1 - Luis Rol?ndez, A1 - Salvador Mir, A1 - Guillaume Prenat, A1 - Ahc?ne Bounceur, PY - 2004 KW - null VL - 1 JA - Design, Automation & Test in Europe Conference & Exhibition ER - | |||
The test of Analogue and Mixed-Signal (AMS) cores requires the use of expensive AMS testers and accessibility to internal analogue nodes. The test cost can be considerably reduced by the use of Built-In-Self-Test (BIST) techniques. One of these techniques consists in generating analogue test signals from digital test patterns (obtained via [Sigma-Delta] modulation) and converting the responses of the analogue modules into digital signatures that are compared with the expected ones. This paper presents an implementation of the analogue test signal generation part that includes programmability of the circuit blocks, leading to an improvement of performance and a reduction of circuit size with respect to previous approaches. A 0.18 ?m CMOS circuit has been designed and fabricated, allowing the generation of test signals ranging from 10 Hz to 1 MHz.
Citation:
Luis Rol?ndez, Salvador Mir, Guillaume Prenat, Ahc?ne Bounceur, "A 0.18 ?m CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns," date, vol. 1, pp.10706, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004
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