Feb. 16, 2004 to Feb. 20, 2004
Kris Tiri , University of California at Los Angeles
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make ?new? compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.
Kris Tiri, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation", DATE, 2004, Proceedings. Design, Automation and Test in Europe Conference and Exhibition, Proceedings. Design, Automation and Test in Europe Conference and Exhibition 2004, pp. 10246, doi:10.1109/DATE.2004.1268856