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Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
Kris Tiri, University of California at Los Angeles
Ingrid Verbauwhede, University of California at Los Angeles
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make ?new? compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.
Citation:
Kris Tiri, Ingrid Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation," date, vol. 1, pp.10246, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004
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