|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits
Munich, Germany
March 03-March 07
ISBN: 0-7695-1870-2
| ASCII Text | x | ||
| Bart De Smedt, Georges Gielen, "HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits," Design, Automation & Test in Europe Conference & Exhibition, vol. 1, pp. 10256, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003. | |||
| BibTex | x | ||
| @article{ 10.1109/DATE.2003.1186395, author = {Bart De Smedt and Georges Gielen}, title = {HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits}, journal ={Design, Automation & Test in Europe Conference & Exhibition}, volume = {1}, year = {2003}, issn = {1530-1591}, pages = {10256}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.1186395}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Design, Automation & Test in Europe Conference & Exhibition TI - HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits SN - 1530-1591 SP EP A1 - Bart De Smedt, A1 - Georges Gielen, PY - 2003 KW - null VL - 1 JA - Design, Automation & Test in Europe Conference & Exhibition ER - | |||
A novel methodology is presented to structured yield-aware synthesis. The trade-off between yield and the unspecified performances is explored along the design space boundaries, while respecting specifications on the other performances. Through the unique combination of multi-objective evolutionary optimization techniques, multi-variate regression modeling and sensitivity-based yield estimation, the designer is given access to this trade-off, all within transistor-level accuracy. Even more, a large reduction in required computer resources is obtained compared to alternative approaches.
Citation:
Bart De Smedt, Georges Gielen, "HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits," date, vol. 1, pp.10256, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003
Usage of this product signifies your acceptance of the Terms of Use.