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2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02)
Paris, France
March 04-March 08
ISBN: 0-7695-1471-5
Table of Contents
Reviewers (PDF)
pp. xxxvi
Plenary - Keynote Session - Moderator: J. da Franca, ChipIdea, PT
Taylor Scanlon, Virtual Silicon Technology, US
pp. 0012
1A: Hot Topic - How to Choose Semiconductor IP? - Organizer: Yervant Zorian, Virage Logic, US - Moderator: Nic Mokhoff, EE Times, US
1B: Formal Verification of Complex Designs - Moderators: L Fix, Intel, ISR; T. Kropf, Bosch, DE
1C: Cooling Layout Arrangements - Moderators: R.H.J.M. Otten, TU Eindhoven, NL; M.D.F. Wong, Texas U, US
1D: Defect Oriented Test - Moderators: J. Segura, Illes Balears U, ES; H. Manhaeve, Q-Star Test, BE
1E: Power Analysis and Management in Networks and Processors - Moderators: E. Macii, Politecnico di Torino, IT; K. Roy, Purdue U, US
2A: Panel - What is the Right IP Business Model?
null
2B: SAT and BDD Techniques -Moderators: T. Shiple, Synopsys, FR; R. Drechsler, Bremen U, DE
2C: Technology and Interconnect Issues in Low Power Design - Moderators: S. Huss, TU Darmstadt, DE; D. Auvergne, LIRMM, F
2D: Advanced Mixed Signal Test - Moderators: J. Huertas, CNM-IMSE, ES; B. Kaminska, Fluence Technology, US
2E: Collaborative Design - Moderators: A. Sauer, FhG EAS/IIS, DE; A. Pawlak, ITE Warsaw, PL
2F: Panel - Who Owns the Platform?
null
3A: Embedded Tutorial - The Need for Infrastructure IP in SoCs
null
3B: Advances in Logic Synthesis -Moderators: M. Berkelaar, Magma Design Automation, NL; W. Kunz, Kaiserslautern U, DE
3C: Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design - Moderators: F. F?rnandez, IMSE-CNM, ES; A. Konczykowska, Alcatel R&I, FR
3D: Hot Topic - EDA Tools for RF: Myth or Reality?
null
3E: Platform-Based Design and Virtual-Component Reuse - Moderators: W. Wolf, Princeton U, US; N. M?rtinez Madrid, FZI Karlsruhe, DE
3F2: Analogue Circuit Characterisation and Simulation - Moderators: A. R?driguez-V?zquez, IMSE-CNM, ES; D. Leenaerts, Philips, NL
4A: Panel - MEDEA+ and ITRS Roadmaps
null
4B: Asynchronous Circuits and Clock Scheduling - Moderators: M. Renaudin, TIMA, Grenoble, FR; L. Lavagno, Politecnico di Torino, IT
4C: Analogue and Mixed-Signal Systems - Moderators: A. Kaiser, ISEN, FR; P. Wambacq, IMEC, BE
4D: BIST Diagnosis and DFT - Moderators: M. Flottes, LIRMM, FR; A. Benso, Politecnico di Torino, IT
4E: Code and Memory Optimization in Co-Design - Moderators: R. Leupers, TU Aachen, DE; R. Ernst, TU Braunschweig, DE
5A: Hot Topic - Network on a Chip - Moderator/Organizer: G. De Micheli, Stanford U, US
5B: Low Power Architectures and Software - Moderators: W. Nebel, OFFIS, DE; M. Miranda, IMEC, BE
5C: Nitty Gritty Details of Layout Design - Moderators: E. Barke, Hannover U, DE; P. Groeneveld, Magma Design Automation, NL
5D: SoC and System Test - Moderators: Y. Zorian, LogicVision, US; D. Gizopoulos, Piraeus U, GR
5E: Modelling and Synthesis of Embedded Systems - Moderators: J. L?pez, Castilla-La Mancha U, ES; F. Rousseau, TIMA, Grenoble, FR
6A: Panel - Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs
null
6B: Reconfigurable Architectures - Moderators: R.. Hartenstein, Kaiserslautern U, DE; U. Kebschull, Leipzig U, DE
6C: Analogue Modelling, Layout and Sizing - Moderators: H. Graeb, TU Munich, DE; G. Gielen, KU Leuven, BE
6D: Test Resource Partitioning for Embedded Cores - Moderators: Z. Peng, Link?ping U, SE; B. Rouzeyre, LIRMM, FR
6E: System Level Simulation and Modelling - Moderators: B. Al-Hashimi, Southampton U, UK; P. Schwarz, FhG IIS/EAS Dresden, DE
6F: Hot Topic - Deep Submicron Design and Timing Closure
null
7A: Panel - Reconfigurable SoC - What Will it Look Like?
null
7B: Layout Aware Logic Synthesis - Moderators: A. Oliveira, INESC, PT; R. Murgai, Fujitsu Labs., US
7C: Buffering and Tapering - Moderators: J. Lienig, Bosch, DE; F. Johannes, TU Munich, DE
7D: Automatic Design Debug and TPG - Moderators: P. Teixeira, INESC-IST, PT; B. Straube, FhG IIS/EAS Dresden, DE
7E: Object Oriented System Specification and Design - Moderators: W. Grass, Passau U, DE; E. Villar, Cantabria U, ES
8A: Hot Topic - UML: Using the Unified Modeling Language for Embedded System Specification - Moderator/Organizer: L. Lavagno, Politecnico di Torino, IT
8B: Real-Time Embedded Systems - Moderators: Z. Peng, Linkoping U, SE; J. Sifakis, VERIMAG, FR
8C: Interconnect Modelling - Moderators: J. Phillips, Cadence Berkeley Labs, US; L. Silveira, IST/INESC, PT
8D: On-Line Testing and Fault Tolerance - Moderators: L. Bouzaida, STMicroelectronics, FR; A. Singh, Auburn U, US
8E: Design Space Evaluation - Moderators: J. Teich, Paderborn U, DE; W. Kruijtzer, Philips Research, NL
9A: Hot Topic - From System Specification to Layout: Seamless Top-Down Design Methods for Analogue and Mixed Signal Applications
null
9B: Architectural Level Synthesis - Moderators: P. Eles, Linkoping U, SE; B. Mesman, Philips/TU Eindhoven, NL
9C: Advanced Linear Modelling Techniques - Moderators: P. Feldmann, Celight Inc, US; G. Vandersteen, IMEC, BE
9D: Memory Testing and ATPG Issues - Moderators: H. Obermeir, Infineon Technologies, DE; M. Sonza Reorda, Politecnico di Torino, IT
9E: Embedded Software Performance Analysis and Optimization - Moderators: H. Hsieh, UC Riverside, US; R. Lauwereins, IMEC, BE
9G: Technical Plenary - 40 Years of EDA - Moderator: A. Jerraya, TIMA, Grenoble, FR
10A: Hot Topic - Design Technology for Networked Reconfigurable FPGA Platforms
null
10B: High-Level Synthesis and Asynchronous Pipelines - Moderators: N. Dutt, UC Irvine, US; M. Renaudin, TIMA, Grenoble, FR
10C: Coupling and Switching Noise Modelling within Integrated Circuits - Moderators: E. Sicard, INSA, FR; G. Vandenbosch, KU Leuven, BE
10D: Panel - Formal Verification Techniques: Industrial Status and Perspectives
null
10E: Power Optimization for Embedded Processors - Moderators: W. Fornaciari, Politecnico di Milano, IT; L. Lavagno, Politecnico di Torino, IT
Poster Sessions
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