Electromigration is caused by high current density stress in metallization patterns and is a major source of break- down in electronic devices. It is therefore an important reliability issue to verify current densities within all stressed metallization patterns. In this paper we propose a new methodology for hierarchical verification of current densities in arbitrarily shaped analog circuit layouts, including a quasi-3D model to verify irregularities such as vias. Our approach incorporates thermal simulation data to account for the temperature dependency of electromigration. The described methodology, which can be integrated into any IC design flow as a design rule check (DRC), has been successfully tested and verified in commercial design flows.