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2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02)
Gate Level Fault Diagnosis in Scan-Based BIST
Paris, France
March 04-March 08
ISBN: 0-7695-1471-5
| ASCII Text | x | ||
| I. Bayraktaroglu, A. Orailoglu, "Gate Level Fault Diagnosis in Scan-Based BIST," Design, Automation & Test in Europe Conference & Exhibition, pp. 0376, 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/DATE.2002.998301, author = {I. Bayraktaroglu and A. Orailoglu}, title = {Gate Level Fault Diagnosis in Scan-Based BIST}, journal ={Design, Automation & Test in Europe Conference & Exhibition}, volume = {0}, year = {2002}, isbn = {0-7695-1471-5}, pages = {0376}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2002.998301}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Design, Automation & Test in Europe Conference & Exhibition TI - Gate Level Fault Diagnosis in Scan-Based BIST SN - 0-7695-1471-5 SP EP A1 - I. Bayraktaroglu, A1 - A. Orailoglu, PY - 2002 VL - 0 JA - Design, Automation & Test in Europe Conference & Exhibition ER - | |||
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test vector information and enables location identification of single stuck-at faults to a neighborhood of a few gates through set operations on small pass/fail dictionaries. The proposed scheme is applicable to multiple stuck-at faults and bridging faults as well. The practical applicability of the suggested ideas is confirmed through numerous experimental runs on all three fault models.
Citation:
I. Bayraktaroglu, A. Orailoglu, "Gate Level Fault Diagnosis in Scan-Based BIST," date, pp.0376, 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002
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