• D
  • DATE
  • 2001
  • Design, Automation, and Test in Europe (DATE '01)
Advanced Search 
Design, Automation, and Test in Europe (DATE '01)
Munich, Germany
March 13-March 16
ISBN: 0-7695-0993-2
Table of Contents
Tutorials (PDF)
pp. xxxiv
Call for Papers DATE 2002
1A: Complementary Approaches to Designing Correct Circuits
Pallab Dasgupta, Indian Institute of Technology
P.P. Chakrabarti, Indian Institute of Technology
Amit Nandi, Indian Institute of Technology
Sekar Krishna, Indian Institute of Technology
Arindam Chakrabarti, Indian Institute of Technology
pp. 0004
1B: New Design Methods with SystemC
Luc Charest, Universit? de Montr?al
Michel Reid, Universit? de Montr?al
E.Mostapha Aboulhamid, Universit? de Montr?al
Guy Bois, Ecole Polytechnique de Montr?al
pp. 0016
George Economakos, National Technical University of Athens
Petros Oikonomakos, National Technical University of Athens
Ioannis Panagopoulos, National Technical University of Athens
Ioannis Poulakis, National Technical University of Athens
George Papakonstantinou, National Technical University of Athens
pp. 0021
1C: Embedded Tutorial---TRP: Integrating Embedded Test and ATE
1E: Embedded Tutorial---Current Trends in the Design of Automotive Electronic Systems
2A: Platforms and IP-Based Design
2B: Approaching Semantics of Design Languages
Wolfgang Mueller, C-LAB/Paderborn University
Juergen Ruf, University of Tuebingen
Dirk Hoffmann, University of Tuebingen
Joachim Gerlach, University of Tuebingen
Thomas Kropf, University of Tuebingen
Wolfgang Rosenstiehl, University of Tuebingen
pp. 0064
2C: BIST and Diagnosis
Alexander Irion, University of Stuttgart
Gundolf Kiefer, University of Stuttgart
Hans-Joachim Wunderlich, University of Stuttgart
Harald Vranken, Philips Research Laboratories
pp. 0086
A. Paschalis, University of Athens
D. Gizopoulos, University of Piraeus
N. Kranitis, II&T, NCSR "Demokritos"
M. Psarakis, II&T, NCSR "Demokritos"
Y. Zorian, LogicVision
pp. 0092
Jin-Fu Li, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 0097
2E: Hot Topic---EUCAR Session
3A: SAT Based Verification Techniques
Evgueni I. Goldberg, Cadence Design Systems
Mukul R. Prasad, University of California, Berkeley
Robert K. Brayton, University of California, Berkeley
pp. 0114
3B: Panel Session---C/C ++
3C: Advances in SoC Testing
Silvia Chiusano, Politecnico di Torino
Stefano Di Carlo, Politecnico di Torino
Paolo Prinetto, Politecnico di Torino
Hans-Joachim Wunderlich, University of Stuttgart
pp. 0156
3E: Panel Session
4A: Analysis of Communication Systems
4B: Design of Low Power Systems I
Cheng-Ta Hsieh, University of Southern California
Lung-sheng Chen, University of Southern California
Massoud Pedram, University of Southern California
pp. 0182
L. Benini, Universit? di Bologna
G. Castelli, Politecnico di Torino
A. Macii, Politecnico di Torino
E. Macii, Politecnico di Torino
M. Poncino, Politecnico di Torino
R. Scarsi, Politecnico di Torino
pp. 0197
4C: Test Generation and Evaluation
Ashish Giani, Rutgers University
Shuo Sheng, Rutgers University
Michael S. Hsiao, Rutgers University
Vishwani D. Agrawal, Bell Labs, Lucent Technologies
pp. 0204
F. Corno, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
G. Squillero, Politecnico di Torino
M. Violante, Politecnico di Torino
pp. 0209
4E: Panel Session
4F: Planning Support
Minghorng Lai, The University of Texas at Austin
D.F. Wong, The University of Texas at Austin
pp. 0228
Chak-Chung Cheung, The Chinese University of HK
Yu-Liang Wu, The Chinese University of HK
David Ihsin Cheng, Ultima Interconnect Technology
pp. 0233
Makoto Saitoh, Tokyo Institute of Technology
Masaaki Azuma, Tokyo Institute of Technology
Atsushi Takahashi, Tokyo Institute of Technology
pp. 0240
5A: Low-Power Channel Decoding and VLIW Architectures
J. Dielissen, Philips Research
J. Van Meerbergen, Philips Research
Marco Bekooij, Philips Research
Françoise Harmsze, Philips Research
Jos Huisken, Philips Research
Albert Van der Werf, Philips Research
Sergej Sawitzki, Technical University Dresden
pp. 0246
M. Sami, Politecnico di Milano
D. Sciuto, Politecnico di Milano
C. Silvano, Politecnico di Milano
V. Zaccaria, Politecnico di Milano
R. Zafalon, STMicroelectronics
pp. 0252
Alexander Worm, University of Kaiserslautern
Holger Lamm, University of Kaiserslautern
Norbert Wehn, University of Kaiserslautern
pp. 0258
5B: Design of Low-Power Systems II
Andrea Acquaviva, DEIS - Universit? di Bologna
Luca Benini, DEIS - Universit? di Bologna
Bruno Riccó, DEIS - Universit? di Bologna
pp. 0273
5C: On-Line Testing Techniques
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
P. Cheynet, Institut National Polytechnique Grenoble
B. Nicolescu, Institut National Polytechnique Grenoble
R. Velazco, Institut National Polytechnique Grenoble
pp. 0297
Michael G. Wahl, Universit?t Siegen,
Christoph Maaß, Universit?t Siegen,
Tony Ambler, University of Texas at Austin,
Mohammed Rahman, Southwest Texas State University
pp. 0302
A. Drozd, Odessa State Polytechnic University
M. Lobachev, Odessa State Polytechnic University
pp. 0307
5E: Design Methodology for PicoRadio Networks
J.L. da Silva Jr, University of California at Berkeley
J. Shamberger, University of California at Berkeley
M.J. Ammer, University of California at Berkeley
C. Guo, University of California at Berkeley
S. Li, University of California at Berkeley
R. Shah, University of California at Berkeley
T. Tuan, University of California at Berkeley
M. Sheets, University of California at Berkeley
J.M. Rabaey, University of California at Berkeley
B. Nikolic, University of California at Berkeley
A. Sangiovanni-Vincentelli, University of California at Berkeley
P. Wright, University of California at Berkeley
pp. 0314
5F: EMC on Chip and High Density Package Level
Chr. Werner, Infineon Technologies
R. Göttsche, Infineon Technologies
A. Wörner, Infineon Technologies
U. Ramacher, Infineon Technologies
pp. 0331
P. Kralicek, Fraunhofer Institute Reliability and Microintegration
W. John, Fraunhofer Institute Reliability and Microintegration
H. Garbe, University of Hannover
pp. 0336
6A: Design Methods for Analog and Mixed Signal Circuits
R. del Río, Instituto de Microelectr?nica de Sevilla
J.M. de la Rosa, Instituto de Microelectr?nica de Sevilla
F. Medeiro, Instituto de Microelectr?nica de Sevilla
B. Pérez-Verdú, Instituto de Microelectr?nica de Sevilla
A. Rodríguez-Vázquez, Instituto de Microelectr?nica de Sevilla
pp. 0348
6B: Issues in Synthesis and Power Optimization
Srinath R. Naidu, Eindhoven University of Technology
E.T.A.F. Jacobs, Eindhoven University of Technology
pp. 0370
Chih-Wei (Jim) Chang, University of California, Santa Barbara
Bo Hu, University of California, Santa Barbara
Malgorzata Marek-Sadowska, University of California, Santa Barbara
pp. 0377
J.A. Espejo, Universidad Carlos III de Madrid
L. Entrena, Universidad Carlos III de Madrid
E. San Millán, Universidad Carlos III de Madrid
E. Olías, Universidad Carlos III de Madrid
pp. 0391
6C: High Level Validation
Zhihong Zeng, University of Massachusetts Amherst
Priyank Kalla, University of Massachusetts Amherst
Maciej Ciesielski, University of Massachusetts Amherst
pp. 0398
F. Ferrandi, Politecnico di Milano
G. Ferrara, Politecnico di Milano
D. Sciuto, Politecnico di Milano
A. Fin, Universita di Verona
F. Fummi, Universita di Verona
pp. 0403
Amjad Hajjar, Colorado State University
Tom Chen, Colorado State University
Isabelle Munn, Colorado State University
Anneliese Andrews, Colorado State University
Maria Bjorkman, Colorado State University
pp. 0411
6E: Hot Topic---Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools
6F: Interconnect Extraction and Modelling
7A: Timing and Parallel Simulation
R. Ubar, Tallinn Technical University,
A. Jutman, Tallinn Technical University,
Z. Peng, Link?ping University
pp. 0460
P. Ruiz de Clavijo Vazquez, Instituto de Microelectronica de Sevilla. CNM
J. Juan-Chico, Instituto de Microelectronica de Sevilla. CNM
M.J. Bellido, Instituto de Microelectronica de Sevilla. CNM
A. Acosta, Instituto de Microelectronica de Sevilla. CNM
M. Valencia, Instituto de Microelectronica de Sevilla. CNM
pp. 0467
Klaus Hering, Chemnitz University of Technology
Jork Loser, Dresden University of Technology
Jens Markwardt, Leipzig University
pp. 0472
Joachim Küter, Infineon Technologies AG
Erich Barke, University of Hannover
pp. 0479
7B: Embedded Tutorial---Low-Power Issues for SOCs
7C: Defect Oriented Testing
Masaki Hashizume, The Univ. of Tokushima
Masahiro Ichimiya, The Univ. of Tokushima
Hiroyuki Yotsuyanagi, The Univ. of Tokushima
Takeomi Tamesada, The Univ. of Tokushima
pp. 0509
Jing Zeng, Motorola ASP Somerset Design Center
Jayanta Bhadra, Motorola ASP Somerset Design Center
Magdy S. Abadir, Motorola ASP Somerset Design Center
Jacob A. Abraham, The University of Texas at Austin
pp. 0514
7E: Embedded Tutorial---CAD for RF Integrated Circuits and Systems
CAD for RF Circuits (Abstract)
Joel Phillips, Cadence Berkeley Laboratories
Jaijeet Roychowdhury, Bell Laboratories
David Long, Bell Laboratories
Alper Demir, Bell Laboratories
Baolin Yang, Cadence Design Systems, Inc.
pp. 0520
7F: Routing Enhancements
Moderators: V. Meyer zu Bexten, Atmel Germany GmbH, D; E. Barke, Hannover U, D
Luca Macchiarulo, Politecnico di Torino
Enrico Macii, Politecnico di Torino
Luca Benini, Universit? di Bologna
pp. 0546
8B: Modelling and Performance Analysis of Embedded Systems
Paolo Giusto, Cadence Design Systems, Inc.
Grant Martin, Cadence Design Systems, Inc.
Ed Harcourt, Cadence Design Systems, Inc.
pp. 0580
8C: Analog and Mixed Signal Testing
F. Azaïs, LIRMM - University of Montpellier II
S. Bernard, LIRMM - University of Montpellier II
Y. Bertrand, LIRMM - University of Montpellier II
M. Renovell, LIRMM - University of Montpellier II
pp. 0590
8E: Panel Session---Managing the SoC Design Challenge with‚ Soft(tm) Hardware
8F: Hardware-Software Architectures and Synthesis
9A: Reconfigurable Computing I
9B: Embedded Software
Andreas Hoffmann, Integrated Signal Processing Systems (ISS)
Achim Nohl, Integrated Signal Processing Systems (ISS)
Stefan Pees, Integrated Signal Processing Systems (ISS)
Gunnar Braun, Integrated Signal Processing Systems (ISS)
Heinrich Meyr, Integrated Signal Processing Systems (ISS)
pp. 0674
C. Kulkarniz, IMEC and Katholieke Universiteit Leuven
F. Catthoory, IMEC and Katholieke Universiteit Leuven
H. de Many, IMEC and Katholieke Universiteit Leuven
C. Ghez, IMEC
M. Miranda, IMEC
pp. 0686
9C: Panel Session---Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design
9E: Hot Topic---Game Processors
9F: Decision Diagrams
Yi-Yu Liu, National Tsing Hua University
TingTing Hwang, National Tsing Hua University
C. L. Liu, National Tsing Hua University
Kuo-Hua Wang, Fu Jen Catholic University
pp. 0708
9L: Friday Keynote Session---Electronic System Design Methodology: Europe's Positioning
10A: Reconfigurable Computing II
10B: Co-Simulation and System Verification Techniques
Jurgen Ruf, University of Tubingen
Dirk W. Hoffmann, University of Tubingen
Thomas Kropf, University of Tubingen
Wolfgang Rosenstiel, University of Tubingen
pp. 0742
10C: Embedded Tutorial ΠAnalog Methods and Tools for SoC Integration
10E: Panel Session---Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration?
10F: Architectural Level Synthesis
Peter Grun, University of California, Irvine
Nikil Dutt, University of California, Irvine
Alex Nicolau, University of California, Irvine
pp. 0778
Poster Session
Usage of this product signifies your acceptance of the Terms of Use.