- D
- DATE
- 2001
- Design, Automation, and Test in Europe (DATE '01)
| | This Publication | | | | | | | |
| | | | Bibliographic References | | | |
| | | | |
Design, Automation, and Test in Europe (DATE '01) Munich, Germany March 13-March 16 ISBN: 0-7695-0993-2 Table of Contents
Call for Papers DATE 2002
 | 1A: Complementary Approaches to Designing Correct Circuits |
| 1B: New Design Methods with SystemC |
Guy Bois, Ecole Polytechnique de Montr?al pp. 0016
| 1C: Embedded Tutorial---TRP: Integrating Embedded Test and ATE |
| 1E: Embedded Tutorial---Current Trends in the Design of Automotive Electronic Systems |
| 2A: Platforms and IP-Based Design |
| 2B: Approaching Semantics of Design Languages |
| 2C: BIST and Diagnosis |
| 2E: Hot Topic---EUCAR Session |
| 3A: SAT Based Verification Techniques |
| 3B: Panel Session---C/C ++ |
| 3C: Advances in SoC Testing |
| 3E: Panel Session |
| 4A: Analysis of Communication Systems |
| 4B: Design of Low Power Systems I |
| 4C: Test Generation and Evaluation |
| 4E: Panel Session |
| 4F: Planning Support |
| 5A: Low-Power Channel Decoding and VLIW Architectures |
| 5B: Design of Low-Power Systems II |
| 5C: On-Line Testing Techniques |
P. Cheynet, Institut National Polytechnique Grenoble
R. Velazco, Institut National Polytechnique Grenoble pp. 0297
A. Drozd, Odessa State Polytechnic University pp. 0307
| 5E: Design Methodology for PicoRadio Networks |
C. Guo, University of California at Berkeley
S. Li, University of California at Berkeley
R. Shah, University of California at Berkeley
T. Tuan, University of California at Berkeley
M. Sheets, University of California at Berkeley
P. Wright, University of California at Berkeley pp. 0314
| 5F: EMC on Chip and High Density Package Level |
P. Kralicek, Fraunhofer Institute Reliability and Microintegration
W. John, Fraunhofer Institute Reliability and Microintegration pp. 0336
| 6A: Design Methods for Analog and Mixed Signal Circuits |
R. del Río, Instituto de Microelectr?nica de Sevilla
F. Medeiro, Instituto de Microelectr?nica de Sevilla pp. 0348
| 6B: Issues in Synthesis and Power Optimization |
Bo Hu, University of California, Santa Barbara pp. 0377
E. Olías, Universidad Carlos III de Madrid pp. 0391
| 6C: High Level Validation |
| 6E: Hot Topic---Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools |
| 6F: Interconnect Extraction and Modelling |
| 7A: Timing and Parallel Simulation |
R. Ubar, Tallinn Technical University, pp. 0460
A. Acosta, Instituto de Microelectronica de Sevilla. CNM
M. Valencia, Instituto de Microelectronica de Sevilla. CNM pp. 0467
| 7B: Embedded Tutorial---Low-Power Issues for SOCs |
| 7C: Defect Oriented Testing |
Jing Zeng, Motorola ASP Somerset Design Center pp. 0514
| 7E: Embedded Tutorial---CAD for RF Integrated Circuits and Systems |
| 7F: Routing Enhancements |
| Moderators: V. Meyer zu Bexten, Atmel Germany GmbH, D; E. Barke, Hannover U, D |
| 8B: Modelling and Performance Analysis of Embedded Systems |
| 8C: Analog and Mixed Signal Testing |
F. Azaïs, LIRMM - University of Montpellier II pp. 0590
| 8E: Panel Session---Managing the SoC Design Challenge with‚ Soft(tm) Hardware |
| 8F: Hardware-Software Architectures and Synthesis |
Alex Doboli, State University of New York (SUNY) at Stony Brook pp. 0612
| 9A: Reconfigurable Computing I |
| 9B: Embedded Software |
Achim Nohl, Integrated Signal Processing Systems (ISS)
Stefan Pees, Integrated Signal Processing Systems (ISS) pp. 0674
H. de Many, IMEC and Katholieke Universiteit Leuven pp. 0686
| 9C: Panel Session---Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design |
| 9E: Hot Topic---Game Processors |
| 9F: Decision Diagrams |
| 9L: Friday Keynote Session---Electronic System Design Methodology: Europe's Positioning |
| 10A: Reconfigurable Computing II |
| 10B: Co-Simulation and System Verification Techniques |
| 10C: Embedded Tutorial ΠAnalog Methods and Tools for SoC Integration |
| 10E: Panel Session---Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration? |
| 10F: Architectural Level Synthesis |
| Poster Session | Usage of this product signifies your acceptance of the Terms of Use.
| | | | | | | |
