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Design, Automation and Test in Europe (DATE '00) Paris, France March 27-March 30 ISBN: 0-7695-0537-6 Table of Contents
 | Plenary—Keynote Session |
Connected, Smart Devices 3/4: Computing Beyond the Desktop
| 1A: Embedded Software Generation |
Embedded Software Generation
| 1B: Low-Power Issues in System-Level Design |
Low-Power Issues in System-Level Design
Sujit Dey, University of California at San Diego pp. 27
| 1C: Circuit Analysis and Synthesis |
Circuit Analysis and Synthesis
R. Schwencker, Infineon Technologies and Technical University of Munich pp. 42
O. Guerra, Centro Nacional de Microelectr?nica
E. Roca, Centro Nacional de Microelectr?nica pp. 48
Jacky Porte, Ecole Nationale Superieure des Telecommunications pp. 53
| 1D: Embedded Tutorial — Design Practices for Better Reliability and Yield |
Embedded Tutorial — Design Practices for Better Reliability and Yield
| 2A: Embedded Tutorial — System Level Design Using C++ |
Embedded Tutorial — System Level Design Using C++
| 2B: IP and Design Reuse |
Hugo de Man, IMEC and Katholieke Universiteit at Leuven pp. 92
| 2C: Layout |
Ruiqi Tian, University of Texas at Austin and Motorola Computational Technology Lab pp. 106
| 2D: Heterogeneous Aspects in SOC Testing |
Heterogeneous Aspects in SOC Testing
Sule Ozev, University of California at San Diego pp. 128
Hiroshi Date, Institute of Systems &Information Technologies pp. 134
| 3A: System Specification |
| 3B: Implementation of Telecom Systems |
Implementation of Telecom Systems
| 3C: Logic Synthesis: Combination |
Logic Synthesis: Combination
| 3D: BIST for Mixed-Signal Applications |
BIST for Mixed-Signal Applications
| 4A: Decision Diagram Based Methods |
Decision Diagram Based Methods
| 4B: Multi-Processor Architectures and Design Methods |
Multi-Processor Architectures and Design Methods
| 4C: Logic Synthesis: Performance Optimization |
Logic Synthesis: Performance Optimization
| 4D: TPG and Diagnosis in BIST |
TPG and Diagnosis in BIST
| 5A: Architectural-Level Synthesis |
Architectural-Level Synthesis
| 5B: Analysis of Communication Circuits |
Analysis of Communication Circuits
| 5C: Logic Synthesis: Covering and PTL Circuits |
Logic Synthesis: Covering and PTL Circuits
| 5D: Delay and Functional Testing |
Delay and Functional Testing
| 6A: Co-Synthesis of Embedded Systems |
Co-Synthesis of Embedded Systems
| 6B: Hot Topic |
| 6C: Wire Performance |
| 6D: Analogue Aspects of System Testing |
Analogue Aspects of System Testing
| 7A: Abstraction Techniques |
| 7B: Panel Session — A Design Automation Roadmap for Europe |
| 7C: Interconnect Modelling and Analysis |
Interconnect Modelling and Analysis
Lei He, University of Wisconsin at Madison pp. 522
| 7D: Mixed A/D System Design |
| 8A: Scheduling and Timing Analysis for Real-Time Embedded Systems |
Scheduling and Timing Analysis for Real-Time Embedded Systems
| 8B: Hot Topic |
| 8D: Dependability Issues in Advanced ICs and Systems |
Dependability Issues in Advanced ICs and Systems
D. Weiler, Fraunhofer Institute of Microelectronic Circuits and Systems
O. Machul, Fraunhofer Institute of Microelectronic Circuits and Systems
B. J. Hosticka, Fraunhofer Institute of Microelectronic Circuits and Systems pp. 599
| 9A: High-Level Power Optimization |
High-Level Power Optimization
N. Wehn, University of Kaiserslautern pp. 624
| 9B: Panel Session |
The Optimal Architecture Platform for System Design
| 9C: Embedded Tutorial |
| 9D: Defect Oriented Test |
| 10A: Simulation and Emulation |
| 10B: Embedded System Design Frameworks |
Embedded System Design Frameworks
Martyn Edwards, University of Manchester Institute of Science and Technology
Peter Green, University of Manchester Institute of Science and Technology pp. 692
| 10D: Power and Cost Issues in Testing |
Power and Cost Issues in Testing
| Poster Papers |
F. Medeiro, Centro Nacional de Microelectr?nica at Sevilla pp. 739
Sunho Chang, Korea Advanced Institute of Science and Technology
Jong-Sun Kim, Korea Advanced Institute of Science and Technology
Lee-Sup Kim, Korea Advanced Institute of Science and Technology pp. 746
A. Núñez, University of Las Palmas de Gran Canaria
J. Sosa, University of Las Palmas de Gran Canaria pp. 760 Usage of this product signifies your acceptance of the Terms of Use.
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