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Design, Automation and Test in Europe (DATE '00)
Paris, France
March 27-March 30
ISBN: 0-7695-0537-6
Table of Contents
Reviewers (PDF)
pp. xxvii
Plenary—Keynote Session
Connected, Smart Devices 3/4: Computing Beyond the Desktop
1A: Embedded Software Generation
Embedded Software Generation
1B: Low-Power Issues in System-Level Design
Low-Power Issues in System-Level Design
Yung-Hsiang Lu, Stanford University
Eui-Young Chung, Stanford University
Tajana Simunic, Stanford University
Giovanni de Micheli, Stanford University
Luca Benini, Universita di Bologna
pp. 20
Marcello Lajolo, Politecnico di Torino
Sujit Dey, University of California at San Diego
Luciano Lavagno, Universit? di Udine
pp. 27
L. Benini, Universit? di Bologna
G. Castelli, Politecnico di Torino
A. Macii, Politecnico di Torino
E. Macii, Politecnico di Torino
M. Poncino, Politecnico di Torino
R. Scarsi, Politecnico di Torino
pp. 35
1C: Circuit Analysis and Synthesis
Circuit Analysis and Synthesis
R. Schwencker, Infineon Technologies and Technical University of Munich
F. Schenkel, Infineon Technologies
H. Graeb, Infineon Technologies
K. Antreich, Infineon Technologies
pp. 42
O. Guerra, Centro Nacional de Microelectr?nica
E. Roca, Centro Nacional de Microelectr?nica
F.V. Fernández, Centro Nacional de Microelectr?nica
A. Rodríguez-Vázquez, Centro Nacional de Microelectr?nica
pp. 48
Mohamed Dessouky, Universit? Paris VI
Marie-Minerve Louërat, Universit? Paris VI
Jacky Porte, Ecole Nationale Superieure des Telecommunications
pp. 53
1D: Embedded Tutorial — Design Practices for Better Reliability and Yield
Embedded Tutorial — Design Practices for Better Reliability and Yield
2A: Embedded Tutorial — System Level Design Using C++
Embedded Tutorial — System Level Design Using C++
2B: IP and Design Reuse
IP and Design Reuse
Roman L. Lysecky, University of California at Riverside
Frank Vahid, University of California at Riverside
Tony D. Givargis, University of California at Riverside
pp. 84
Frederik Vermeulen, IMEC and Katholieke Universiteit at Leuven
Francky Catthoor, IMEC and Katholieke Universiteit at Leuven
Hugo de Man, IMEC and Katholieke Universiteit at Leuven
pp. 92
2C: Layout
Layout
Xiaoping Tang, University of Texas at Austin
D.F. Wong, University of Texas at Austin
Ruiqi Tian, University of Texas at Austin and Motorola Computational Technology Lab
pp. 106
2D: Heterogeneous Aspects in SOC Testing
Heterogeneous Aspects in SOC Testing
Sule Ozev, University of California at San Diego
Ismet Bayraktaroglu, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 128
3A: System Specification
System Specification
3B: Implementation of Telecom Systems
Implementation of Telecom Systems
F. Viglione, Politecnico di Torino
G. Masera, Politecnico di Torino
G. Piccinini, Politecnico di Torino
M. Ruo Roch, Politecnico di Torino
M. Zamboni, Politecnico di Torino
pp. 176
3C: Logic Synthesis: Combination
Logic Synthesis: Combination
3D: BIST for Mixed-Signal Applications
BIST for Mixed-Signal Applications
Jiun-Lang Huang, University of California at Santa Barbara
Chee-Kian Ong, University of California at Santa Barbara
Kwang-Ting Cheng, University of California at Santa Barbara
pp. 216
Yun-Che Wen, National Cheng Kung University
Kuen-Jong Lee, National Cheng Kung University
pp. 221
4A: Decision Diagram Based Methods
Decision Diagram Based Methods
Priyank Kalla, University of Massachusetts at Amherst
Zhihong Zeng, University of Massachusetts at Amherst
Maciej Ciesielski, University of Massachusetts at Amherst
Chilai Huang, Avery Design Systems Incorporated
pp. 232
Praveen Yalagandula, University of Texas at Austin
Adnan Aziz, University of Texas at Austin
Vigyan Singhal, Tempus Fugit Incorporated
pp. 237
4B: Multi-Processor Architectures and Design Methods
Multi-Processor Architectures and Design Methods
Françoise Harmsze, Eindhoven University of Technology
Adwin Timmer, Eindhoven University of Technology
Jef van Meerbergen, Eindhoven University of Technology
pp. 257
4C: Logic Synthesis: Performance Optimization
Logic Synthesis: Performance Optimization
Wave Steered FSMs (Abstract)
Luca Macchiarulo, University of California, Santa Barbara
Shih-Ming Shu, University of California, Santa Barbara
Malgorzata Marek-Sadowska, University of California, Santa Barbara
pp. 270
4D: TPG and Diagnosis in BIST
TPG and Diagnosis in BIST
Silvia Cataldo, Politecnico di Torino
Silvia Chiusano, Politecnico di Torino
Paolo Prinetto, Politecnico di Torino
Hans-Joachim Wunderlich, University of Stuttgart
pp. 292
5A: Architectural-Level Synthesis
Architectural-Level Synthesis
Oliver Bringmann, Forschungszentrum Informatik and Universit?t Tuebingen
Wolfgang Rosenstiel, Forschungszentrum Informatik and Universit?t Tuebingen
Carsten Menn, Forschungszentrum Informatik
pp. 326
5B: Analysis of Communication Circuits
Analysis of Communication Circuits
M.M. Gourary, IPPM, Russian Academy of Sciences
S.G. Rusakov, IPPM, Russian Academy of Sciences
S.L. Ulyanov, IPPM, Russian Academy of Sciences
M.M. Zharov, IPPM, Russian Academy of Sciences
K.K. Gullapalli, Motorola Incorporated
B.J. Mulvaney, Motorola Incorporated
pp. 345
5C: Logic Synthesis: Covering and PTL Circuits
Logic Synthesis: Covering and PTL Circuits
Roberto Cordone, Politecnico di Milano
Fabrizio Ferrandi, Politecnico di Milano
Donatella Sciuto, Politecnico di Milano
Roberto Wolfler Calvo, Joint Research Center - Ispra
pp. 364
5D: Delay and Functional Testing
Delay and Functional Testing
6A: Co-Synthesis of Embedded Systems
Co-Synthesis of Embedded Systems
Maria Luisa López-Vallejo, Universidad Politecnica Madrid
Jesus Grajal, Universidad Politecnica Madrid
Juan Carlos López, Universidad Castilla-La Mancha
pp. 411
6B: Hot Topic
Hot Topic
6C: Wire Performance
Wire Performance
I-Min Liu, University of Texas at Austin
Adnan Aziz, University of Texas at Austin
D.F. Wong, University of Texas at Austin
pp. 436
6D: Analogue Aspects of System Testing
Analogue Aspects of System Testing
Uros Kac, Jozef Stefan Institute
Franc Novak, Jozef Stefan Institute
Srecko Macek, Jozef Stefan Institute
pp. 463
7A: Abstraction Techniques
Abstraction Techniques
7B: Panel Session — A Design Automation Roadmap for Europe
Panel Session
7C: Interconnect Modelling and Analysis
Interconnect Modelling and Analysis
Norman Chang, Hewlett-Packard Laboratories
Shen Lin, Hewlett-Packard Laboratories
O. Sam Nakagawa, Hewlett-Packard Laboratories
Weize Xie, Hewlett-Packard Laboratories
Lei He, University of Wisconsin at Madison
pp. 522
Chauchin Su, National Central University
Yue-Tsang Chen, National Central University
Mu-Jeng Huang, National Central University
Gen-Nan Chen, National Central University
Chung-Len Lee, National Chiao-Tung University
pp. 527
7D: Mixed A/D System Design
Mixed A/D System Design
8A: Scheduling and Timing Analysis for Real-Time Embedded Systems
Scheduling and Timing Analysis for Real-Time Embedded Systems
8B: Hot Topic
Hot Topic
8D: Dependability Issues in Advanced ICs and Systems
Dependability Issues in Advanced ICs and Systems
M. Lajolo, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
L. Lavagno, Universit? di Udine
pp. 586
D. Weiler, Fraunhofer Institute of Microelectronic Circuits and Systems
O. Machul, Fraunhofer Institute of Microelectronic Circuits and Systems
D. Hammerschmidt, Fraunhofer Institute of Microelectronic Circuits and Systems
B. J. Hosticka, Fraunhofer Institute of Microelectronic Circuits and Systems
pp. 599
9A: High-Level Power Optimization
High-Level Power Optimization
Dinesh Ramanathan, University of California at Irvine
Rajesh Gupta, University of California at Irvine
pp. 606
Cheng-Ta Hsieh, University of Southern California
Massoud Pedram, University of Southern California
pp. 612
M. Münch, University of Kaiserslautern
N. Wehn, University of Kaiserslautern
B. Wurth, Infineon Technologies AG
R. Mehra, Synopsys Incorporated
J. Sproch, Synopsys Incorporated
pp. 624
9B: Panel Session
The Optimal Architecture Platform for System Design
Rolf Ernst, Technical University of Braunschweig
Grand Martin, Cadence
Oz Levia, Improv Systems Incorporated
Pierre Paulin, STMicroelectronics
Vassiliadis Stamatis, Technical University of Delft
Kees Vissers, Philips Research
pp. 634
9C: Embedded Tutorial
How Thin is the Ice?
9D: Defect Oriented Test
Defect Oriented Test
10A: Simulation and Emulation
Simulation and Emulation
Sungjoo Yoo, Seoul National University
Jong-Eun Lee, Seoul National University
Jinyong Jung, Seoul National University
Kyungseok Rha, Seoul National University
Youngchul Cho, Seoul National University
Kiyoung Choi, Seoul National University
pp. 663
10B: Embedded System Design Frameworks
Embedded System Design Frameworks
Martyn Edwards, University of Manchester Institute of Science and Technology
Peter Green, University of Manchester Institute of Science and Technology
pp. 692
10D: Power and Cost Issues in Testing
Power and Cost Issues in Testing
Juin-Ming Lu, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 710
Poster Papers
Tajana Simunic, Stanford University
Luca Benini, Stanford University
Peter Glynn, University of Bologna
Giovanni de Micheli, University of Bologna
pp. 736
F.M. Pérez-Montes, Centro Nacional de Microelectr?nica at Sevilla
F. Medeiro, Centro Nacional de Microelectr?nica at Sevilla
R. Domínguez-Castro, Centro Nacional de Microelectr?nica at Sevilla
F.V. Fernández, Centro Nacional de Microelectr?nica at Sevilla
A. Rodríguez-Vázquez, Centro Nacional de Microelectr?nica at Sevilla
pp. 739
Peter Bach, Universit?t des Saarlandes
Michael Bosch, Universit?t des Saarlandes
pp. 741
Sunho Chang, Korea Advanced Institute of Science and Technology
Jong-Sun Kim, Korea Advanced Institute of Science and Technology
Lee-Sup Kim, Korea Advanced Institute of Science and Technology
pp. 746
Ashok Halambi, University of California at Irvine
Radu Cornea, University of California at Irvine
Peter Grun, University of California at Irvine
Nikil Dutt, University of California at Irvine
Alex Nicolau, University of California at Irvine
pp. 748
Congguang Yang, University of Massachusetts at Amherst
Maciej Ciesielski, University of Massachusetts at Amherst
pp. 750
E. Dubrova, Royal Institute of Technology
P. Ellervee, Royal Institute of Technology
D.M. Miller, University of Victoria
J.C. Muzio, University of Victoria
pp. 751
José Manuel Moya, Universidad de Castilla-La Mancha
Francisco Moya, Universidad de Castilla-La Mancha
Juan Carlos López, Universidad de Castilla-La Mancha
Santiago Domínguez, Universidad Polit?cnica de Madrid
pp. 753
Hilary Kahn, University of Manchester
Andy Carpenter, University of Manchester
Nigel Whitaker, University of Manchester
pp. 755
D. Gizopoulos, University of Piraeus
N. Kranitis, II&T, NCSR "Demokritos"
M. Psarakis, II&T, NCSR "Demokritos"
A. Paschalis, University of Athens
Y. Zorian, LogicVision
pp. 757
Jens Schönherr, Fraunhofer-Institut f?r Integrierte Schaltungen
Bernd Straube, Fraunhofer-Institut f?r Integrierte Schaltungen
pp. 759
S. Nooshabadi, University of Tasmania
J.A. Montiel-Nelson, University of Las Palmas de Gran Canaria
A. Núñez, University of Las Palmas de Gran Canaria
R. Sarmiento, University of Las Palmas de Gran Canaria
J. Sosa, University of Las Palmas de Gran Canaria
pp. 760
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