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Design, Automation and Test in Europe (DATE '99)
Munich, Germany
March 09-March 12
ISBN: 0-7695-0078-1
Table of Contents
Tutorials (PDF)
pp. xxviii
Embedded System Design — The European Technology Driver
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1A: Verification of Sequential Circuits
Verification of Secuential Circuits
1B: Architectural Issues in Low Power Design
Architectural Issues in Low Power Design
Enoch Hwang, University of California at Riverside
Frank Vahid, University of California at Riverside
Yu-Chin Hsu, University of California at Riverside
pp. 22
Gerd Jochens, OFFIS Research Institute, Oldenburg
Lars Kruse, OFFIS Research Institute, Oldenburg
Eike Schmidt, OFFIS Research Institute, Oldenburg
Wolfgang Nebel, OFFIS Research Institute, Oldenburg
pp. 29
1C: Design Reuse Repository and IP Architecture
Design Reuse Repository and IP Architecture
2A: High Level Verification
High Level Verification
Stefan Höreth, Siemens Corporate R&D and Darmstadt University of Technology
Rolf Drechsler, Albert-Ludwigs-University
pp. 52
Hans Eveking, Darmstadt University of Technology
Holger Hinrichsen, Darmstadt University of Technology
Gerd Ritter, Darmstadt University of Technology
pp. 59
2B: System-Level Power Optimization
System-Level Power Optimization
Massoud Pedram, University of Southern California
Qing Wu, University of Southern California
pp. 72
Eui-Young Chung, Stanford University
Luca Benini, Universit? di Bologna
Alessandro Bogliolo, Universit? di Bologna
Giovanni de Micheli, Computer System Laboratory
pp. 77
Rajeev Murgai, Fujitsu Laboratories of America, Inc.
Masahiro Fujita, Fujitsu Laboratories of America, Inc.
pp. 82
2C: Reconfigurability and Other Issues in Embedded System Design
Reconfigurability and Other Issues in Embedded System Design
2E: Embedded Core Test Approaches
Embedded Core Test Approaches
D. Nikolos, University of Patras and Computer Technology Institute
H. T. Vergos, University of Patras and Computer Technology Institute
Th. Haniotakis, ISD S.A
Y. Tsiatouhas, ISD S.A
pp. 112
A. Paschalis, Institute of Informatics & Telecommunications, NCSR "Demokritos"
N. Kranitis, Institute of Informatics & Telecommunications, NCSR "Demokritos"
M. Psarakis, Institute of Informatics & Telecommunications, NCSR "Demokritos"
D. Gizopoulos, 4PLUS Technologies
Y. Zorian, LogicVision
pp. 117
3A: Use of Combinational Verification
Use of Combinational Verification
Rajarshi Mukherjee, Fujitsu Laboratories of America
Jawahar Jain, Fujitsu Laboratories of America
Koichiro Takayama, Fujitsu Laboratories of America
Masahiro Fujita, Fujitsu Laboratories of America
Jacob A. Abraham, University of Texas at Austin
Donald S. Fussell, University of Texas at Austin
pp. 132
Stefan Hendricx, IMEC vzw/Katholieke Universiteit Leuven
Luc Claesen, IMEC vzw/Katholieke Universiteit Leuven
pp. 150
3B: Gate Level Power Estimation and Optimization
Gate Level Power Estimation and Optimization
Ki-Wook Kim, University of Illinois at Urbana-Champaign
Sung-Mo Kang, University of Illinois at Urbana-Champaign
Ting Ting Hwang, Tsing Hua University
C.L. Liu, Tsing Hua University
pp. 158
L. Benini, Universit? di Bologna
G. de Micheli, Stanford University
A. Macii, Politecnico di Torino
E. Macii, Politecnico di Torino
M. Poncino, Politecnico di Torino
R. Scarsi, Politecnico di Torino
pp. 163
3C: Special Session — Virtual Socket Interface Alliance
Special Session
Ralf Seepold, Forschungszentrum Informatik an der Universit?t Karlsruhe (FZI)
pp. 182
3D: Speakers
VSI Builds Momentum to Solve Design Reuse Imperative
The VSI System-Level Perspective on the Mix and Match of Virtual Components
Introduction to Virtual Component Interface
3E: Fault Diagnosis Techniques for Analogue Circuits
Fault Diagnosis Techniques for Analogue Circuits
Erika F. Cota, Universidade Federal do Rio Grande do Sul
Luigi Carro, Universidade Federal do Rio Grande do Sul
Marcelo Lubaszewski, Universidade Federal do Rio Grande do Sul
pp. 184
4A: Resource Sharing in Architectural Synthesis
Resource Sharing in Architectural Synthesis
4B: Mixed Signal Characterization and Test
Mixed Signal Characterization Test
Franc Novak, Jozef Stefan Institute
Bojan Hvala, University of Maribor
Sandi Klavzar, University of Maribor
pp. 249
4C: System Design Methodologies: Modelling, Analysis, Refinement and Synthesis
System Design Methodologies: Modelling, Analysis, Refinement and Synthesis
4E: High Level Test Synthesis
High Level Test Synthesis
Yiorgos Makris, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 283
5A: High-Level System Simulation
High-Level System Simulation
Katsuyuki Ochiai, NTT Human Interface Laboratories
Hiroe Iwasaki, NTT Human Interface Laboratories
Jiro Naganuma, NTT Human Interface Laboratories
Makoto Endo, NTT Human Interface Laboratories
Takeshi Ogura, NTT Human Interface Laboratories
pp. 303
Bassam Tabbara, University of California at Berkeley
Marco Sgroi, University of California at Berkeley
Alberto Sangiovanni-Vincentelli, University of California at Berkeley
Luciano Lavagno, Cadence Berkeley Labs
pp. 309
5B: Analogue Circuit Sizing and Synthesis
Analogue Circuit Sizing and Synthesis
C. Verhoeven, Delft University of Technology
A. Van Staveren, Delft University of Technology
pp. 318
R. Schwencker, Institute of Electronic Design Automation and Technical University of Munich
J. Eckmueller, Technical University of Munich
H. Graeb, Institute of Electronic Design Automation
K. Antreich, Institute of Electronic Design Automation
pp. 323
5C: VHDL-AMS and HDL Interoperability
VHDL-AMS and HDL Interoperability
5E: Transistor Level Test
Transistor Level Test
6A: Hot Topic — Hardware Synthesis from C/C++ Models
Hot Topic
6B: Analogue Modelling and Simulation
Analogue Modelling and Simulation
E. Lauwers, Katholieke Universiteit Leuven
G. Gielen, Katholieke Universiteit Leuven
pp. 401
O. Guerra, Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
J. D. Rodríguez-García, Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
E. Roca, Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
F. V. Fernández, Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
A. Rodríguez-Vázquez, Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
pp. 412
6C: Hot Topic — Chip Package Co-Design
Chip Package Co-Design
6E: Panel
Scaling Towards Nanometer Technologies: Design for Test Challenges
7A: Functional Verification
Functional Verification
7B: Bit-Level Logic and Analogue Simulation
Bit-Level Logic and Analogue Simulation
Raimund Ubar, Tallinn Technical University
Jaan Raik, Tallinn Technical University
Adam Morawiec, TIMA Laboratory
pp. 454
M. Bühler, University of Stuttgart
M. Papesch, University of Stuttgart
K. Kapp, University of Stuttgart
U.G. Baitinger, University of Stuttgart
pp. 459
7E: Partial and Boundary Scan Test
Partial and Boundary Scan Test
Xijiang Lin, Mentor Graphics Corporation
Irith Pomeranz, University of Iowa
Sudhakar M. Reddy, University of Iowa
pp. 468
8A: New Languages for System Specification and Design
New Languages for System Specification and Design
8B: Circuit Analysis and Design
Circuit Analysis and Design
Heiko Holzheuer, C-LAB, Cooperation of Universit?t-GH Paderborn and Siemens AG
pp. 498
Lluis Ribas, Autonomous University of Barcelona (UAB)
Jordi Carrabina, Autonomous University of Barcelona (UAB)
pp. 503
J. A. Montiel-Nelson, University of Las Palmas de Gran Canaria
S. Nooshabadi, University of Las Palmas de Gran Canaria
V. de Armas, University of Las Palmas de Gran Canaria
R. Sarmiento, University of Las Palmas de Gran Canaria
A. Nunez, University of Las Palmas de Gran Canaria
pp. 509
8C: Logic Synthesis
Logic Synthesis
Enrique San Millán, Universidad Carlos III de Madrid
Luis Entrena, Universidad Carlos III de Madrid
José A. Espejo, Universidad Carlos III de Madrid
Silvia Chiusano, Politecnico di Torino
Fulvio Corno, Politecnico di Torino
pp. 516
8E: IDDX Testing and Defect Modelling
IDDX Testing and Defect Modelling
V. Stopjaková, Slovak Technical University
H. Manhaeve, Department of Microelectronics, KHBO
M. Sidiropulos, Technical University of Brno
pp. 538
9A: HW/SW Interface Synthesis and Partitioning
HW/SW Interface Synthesis and Partitioning
9B: Physical Design Issues
Physical Design Issues
Helena Krupnova, Institut National Polytechnique de Grenoble
Gabriele Saucier, Institut National Polytechnique de Grenoble
pp. 587
9C: Reliability and Symmetry in Architectural Synthesis
Reliability and Symmetry in Architectural Synthesis
Samuel N. Hamilton, University of California at San Diego
Alex Orailoglu, University of California at San Diego
Andre Hertwig, University GH Siegen
pp. 596
C.A.J. Van Eijk, Eindhoven University of Technology
E.T.A.F. Jacobs, Eindhoven University of Technology
B. Mesman, Eindhoven University of Technology and Philips Research Laboratories
A.H. Timmer, Philips Research Laboratories
pp. 602
9D: Panel — Single Chip or Hybrid System Integration?
Panel
9E: Testing Regular Structures and Delay Faults
Testing Regular Structures and Delay Faults
10A: Retiming
Retiming
10B: Modelling of Interconnects
Modelling of Interconnects
Lun Ye, Bell Laboratories
Foong-Charn Chang, Bell Laboratories
Peter Feldmann, Bell Laboratories
Rakesh Chadha, Bell Laboratories
Nagaraj Ns, Texas Instruments Inc.
Frank Cano, Texas Instruments Inc.
pp. 658
Janet M. Wang, University of California at Berkeley
Qingjian Yu, University of California at Berkeley
Ernest S. Kuh, University of California at Berkeley
pp. 664
10C: Design Reuse Methodologies for Virtual Components and IP
Design Reuse Methodologies for Virtual Components and IP
10D: Embedded Tutorial — Multilanguage System Design
Embedded Tutorial—Multilanguage System Design
Ahmed Jerraya, TIMA Laboratory
Rolf Ernst, Technical University Braunschweig
pp. 696
10E: RAM BIST
RAM BIST
11B: Panel — Java, VHDL-AMS, Ada or C for System Level Specifications?
Panel
Eduard Moser, Robert Bosch GmbH, FV/FLI
Wolfgang Nebel, Universit?t Oldenburg and OFFIS
pp. 721
11C: Hot Topic — IP and Reuse
IP and Reuse
11D: Special Session—Large European Programs in Microelectronic System and Circuit Design
Special Session
11E: Speakers
MEDEA—The Microelectronic Development Program for European Applications—Status of the Design-Oriented Program and Future Plan
Electronic Systems Design in the IST Program
ITEA—Information Technology and European Advancement
11F: Sequential Circuit Test Generation
Sequential Circuit Test Generation
M. Konijnenburg, Delft University of Technology
J. Van der Linden, Delft University of Technology
A. van de Goor, Delft University of Technology
pp. 741
Yanti Santoso, University of Illinois
Matthew Merten, University of Illinois
Elizabeth M. Rudnick, University of Illinois
Miron Abramovici, Bell Labs - Lucent Technologies
pp. 747
Posters
A. Maamar, The University of Newcastle upon Tyne
G. Russell, The University of Newcastle upon Tyne
pp. 770
Jung Hyun Choi, Federal University of Rio Grande do Sul - UFRGS
Sergio Bampi, Federal University of Rio Grande do Sul - UFRGS
pp. 776
C. Alippi, Politecnico di Milano
W. Fornaciari, Politecnico di Milano
L. Pozzi, Politecnico di Milano
M. Sami, Politecnico di Milano
pp. 778
Françoise Martinolle, Cadence Design Systems, Inc.
Charles Dawson, Cadence Design Systems, Inc.
Debra Corlette, Cadence Design Systems, Inc.
Mike Floyd, Cadence Design Systems, Inc.
pp. 788
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