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Design, Automation & Test in Europe Conference & Exhibition (1999)
Munich, Germany
Mar. 9, 1999 to Mar. 12, 1999
ISBN: 0-7695-0078-1
TABLE OF CONTENTS
Reviewers (PDF)
pp. xxv
pp. xxvii
Tutorials (PDF)
pp. xxviii
Embedded System Design — The European Technology Driver
null (PDF)
pp. null
1A: Verification of Sequential Circuits
Gianpiero Cabodi , Politecnico di Torino
Claudio Passerone , Politecnico di Torino
Stefano Quer , Politecnico di Torino
pp. 8
Youpyo Hong , Synopsys, Inc
Peter A. Beerel , University of Southern California
pp. 13
1B: Architectural Issues in Low Power Design
Enoch Hwang , University of California at Riverside
Frank Vahid , University of California at Riverside
Yu-Chin Hsu , University of California at Riverside
pp. 22
Lars Kruse , OFFIS Research Institute, Oldenburg
Eike Schmidt , OFFIS Research Institute, Oldenburg
Wolfgang Nebel , OFFIS Research Institute, Oldenburg
pp. 29
1C: Design Reuse Repository and IP Architecture
2A: High Level Verification
Stefan Höreth , Siemens Corporate R&D and Darmstadt University of Technology
Rolf Drechsler , Albert-Ludwigs-University
pp. 52
Hans Eveking , Darmstadt University of Technology
Gerd Ritter , Darmstadt University of Technology
pp. 59
2B: System-Level Power Optimization
Massoud Pedram , University of Southern California
Qing Wu , University of Southern California
pp. 72
Luca Benini , Universit? di Bologna
Alessandro Bogliolo , Universit? di Bologna
Giovanni de Micheli , Computer System Laboratory
pp. 77
Rajeev Murgai , Fujitsu Laboratories of America, Inc.
Masahiro Fujita , Fujitsu Laboratories of America, Inc.
pp. 82
2C: Reconfigurability and Other Issues in Embedded System Design
2E: Embedded Core Test Approaches
H. T. Vergos , University of Patras and Computer Technology Institute
Th. Haniotakis , ISD S.A
Y. Tsiatouhas , ISD S.A
pp. 112
N. Kranitis , Institute of Informatics & Telecommunications, NCSR "Demokritos"
M. Psarakis , Institute of Informatics & Telecommunications, NCSR "Demokritos"
D. Gizopoulos , 4PLUS Technologies
A. Paschalis , Institute of Informatics & Telecommunications, NCSR "Demokritos"
pp. 117
3A: Use of Combinational Verification
Jawahar Jain , Fujitsu Laboratories of America
Koichiro Takayama , Fujitsu Laboratories of America
Rajarshi Mukherjee , Fujitsu Laboratories of America
Jacob A. Abraham , University of Texas at Austin
Donald S. Fussell , University of Texas at Austin
pp. 132
Stefan Hendricx , IMEC vzw/Katholieke Universiteit Leuven
pp. 150
3B: Gate Level Power Estimation and Optimization
Ki-Wook Kim , University of Illinois at Urbana-Champaign
Sung-Mo Kang , University of Illinois at Urbana-Champaign
Ting Ting Hwang , Tsing Hua University
C.L. Liu , Tsing Hua University
pp. 158
G. de Micheli , Stanford University
A. Macii , Politecnico di Torino
E. Macii , Politecnico di Torino
M. Poncino , Politecnico di Torino
R. Scarsi , Politecnico di Torino
pp. 163
3C: Special Session — Virtual Socket Interface Alliance
pp. null
Ralf Seepold , Forschungszentrum Informatik an der Universit?t Karlsruhe (FZI)
pp. 182
3D: Speakers
3E: Fault Diagnosis Techniques for Analogue Circuits
Luigi Carro , Universidade Federal do Rio Grande do Sul
Marcelo Lubaszewski , Universidade Federal do Rio Grande do Sul
pp. 184
Alfred V. Gomes , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 189
S. Cherubal , Georgia Institute of Technology
pp. 195
4A: Resource Sharing in Architectural Synthesis
James Smith , Stanford University
Giovanni de Micheli , Stanford University
pp. 217
4B: Mixed Signal Characterization and Test
Z.R. Yang , University of Southampton
M. Zwolinski , University of Southampton
pp. 244
Bojan Hvala , University of Maribor
Franc Novak , Jozef Stefan Institute
pp. 249
4C: System Design Methodologies: Modelling, Analysis, Refinement and Synthesis
Robert P. Dick , Princeton University
Niraj K. Jha , Princeton University
pp. 263
4E: High Level Test Synthesis
Joan Carletta , Case Western Reserve University
Mehrdad Nourani , Case Western Reserve University
Christos Papachristou , Case Western Reserve University
pp. 278
Yiorgos Makris , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 283
5A: High-Level System Simulation
Hiroe Iwasaki , NTT Human Interface Laboratories
Jiro Naganuma , NTT Human Interface Laboratories
Makoto Endo , NTT Human Interface Laboratories
Katsuyuki Ochiai , NTT Human Interface Laboratories
pp. 303
Marco Sgroi , University of California at Berkeley
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Bassam Tabbara , University of California at Berkeley
pp. 309
5B: Analogue Circuit Sizing and Synthesis
C. Verhoeven , Delft University of Technology
pp. 318
J. Eckmueller , Technical University of Munich
H. Graeb , Institute of Electronic Design Automation
K. Antreich , Institute of Electronic Design Automation
pp. 323
5C: VHDL-AMS and HDL Interoperability
Alex Doboli , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 338
5E: Transistor Level Test
Yvon Savaria , Ecole Polytechnique
Nanhan Xiong , Ecole Polytechnique
Bernard Antaki , Ecole Polytechnique
pp. 360
Michele Favalli , DI - University of Ferrara
Cecilia Metra , DEIS - University of Bologna
pp. 368
D. Niggemeyer , University of Hannover
pp. 376
6A: Hot Topic — Hardware Synthesis from C/C++ Models
Hot Topic (PDF)
pp. null
Giovanni de Micheli , Stanford University
pp. 382
Guido Arnout , CoWare, Inc.
pp. 384
Abhijit Ghosh , Synopsys Inc.
Joachim Kunkel , Synopsys Inc.
Stan Liao , Synopsys Inc.
pp. 387
Kazutoshi Wakabayashi , C&C Media Research Laboratories, NEC Corp.
pp. 390
6B: Analogue Modelling and Simulation
E. Lauwers , Katholieke Universiteit Leuven
G. Gielen , Katholieke Universiteit Leuven
pp. 401
J. D. Rodríguez-García , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
E. Roca , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
F. V. Fernández , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
A. Rodríguez-Vázquez , Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
pp. 412
6C: Hot Topic — Chip Package Co-Design
6E: Panel
7A: Functional Verification
7B: Bit-Level Logic and Analogue Simulation
Raimund Ubar , Tallinn Technical University
Jaan Raik , Tallinn Technical University
Adam Morawiec , TIMA Laboratory
pp. 454
M. Papesch , University of Stuttgart
K. Kapp , University of Stuttgart
U.G. Baitinger , University of Stuttgart
pp. 459
7E: Partial and Boundary Scan Test
Xijiang Lin , Mentor Graphics Corporation
Irith Pomeranz , University of Iowa
Sudhakar M. Reddy , University of Iowa
pp. 468
8A: New Languages for System Specification and Design
8B: Circuit Analysis and Design
Heiko Holzheuer , C-LAB, Cooperation of Universit?t-GH Paderborn and Siemens AG
pp. 498
Lluis Ribas , Autonomous University of Barcelona (UAB)
pp. 503
S. Nooshabadi , University of Las Palmas de Gran Canaria
V. de Armas , University of Las Palmas de Gran Canaria
J. A. Montiel-Nelson , University of Las Palmas de Gran Canaria
A. Nunez , University of Las Palmas de Gran Canaria
pp. 509
8C: Logic Synthesis
pp. null
Luis Entrena , Universidad Carlos III de Madrid
Enrique San Millán , Universidad Carlos III de Madrid
Silvia Chiusano , Politecnico di Torino
Fulvio Corno , Politecnico di Torino
pp. 516
Luís Guerra e Silva , Instituto Superior T?cnico
L. Miguel Silveira , Instituto Superior T?cnico
João Marques-Silva , Instituto Superior T?cnico
pp. 526
Leon Stok , IBM
Mahesh A. Iyer , Synopsys Inc.
pp. 531
8E: IDDX Testing and Defect Modelling
V. Stopjaková , Slovak Technical University
H. Manhaeve , Department of Microelectronics, KHBO
M. Sidiropulos , Technical University of Brno
pp. 538
9A: HW/SW Interface Synthesis and Partitioning
9B: Physical Design Issues
Helena Krupnova , Institut National Polytechnique de Grenoble
pp. 587
9C: Reliability and Symmetry in Architectural Synthesis
Alex Orailoglu , University of California at San Diego
Samuel N. Hamilton , University of California at San Diego
pp. 596
C.A.J. Van Eijk , Eindhoven University of Technology
E.T.A.F. Jacobs , Eindhoven University of Technology
B. Mesman , Eindhoven University of Technology and Philips Research Laboratories
A.H. Timmer , Philips Research Laboratories
pp. 602
Luiz C.V. dos Santos , Eindhoven University of Technology
Jochen A.G. Jess , Eindhoven University of Technology
pp. 609
9D: Panel — Single Chip or Hybrid System Integration?
Panel (PDF)
pp. null
9E: Testing Regular Structures and Delay Faults
S. Tragoudas , The Univerity of Arizona
pp. 631
10A: Retiming
Retiming (PDF)
pp. null
Priyank Kalla , University of Massachusetts at Amherst
Maciej J. Ciesielski , University of Massachusetts at Amherst
pp. 638
Klaus Eckl , Technical University of Munich
Christian Legl , Technical University of Munich
pp. 650
10B: Modelling of Interconnects
Foong-Charn Chang , Bell Laboratories
Peter Feldmann , Bell Laboratories
Rakesh Chadha , Bell Laboratories
Nagaraj Ns , Texas Instruments Inc.
Frank Cano , Texas Instruments Inc.
pp. 658
Qingjian Yu , University of California at Berkeley
Ernest S. Kuh , University of California at Berkeley
pp. 664
10C: Design Reuse Methodologies for Virtual Components and IP
Cristina Barna , Forschungszentrum Informatik
pp. 689
10D: Embedded Tutorial — Multilanguage System Design
Ahmed Jerraya , TIMA Laboratory
Rolf Ernst , Technical University Braunschweig
pp. 696
10E: RAM BIST
RAM BIST (PDF)
pp. null
11B: Panel — Java, VHDL-AMS, Ada or C for System Level Specifications?
Panel (PDF)
pp. null
Eduard Moser , Robert Bosch GmbH, FV/FLI
pp. 721
11C: Hot Topic — IP and Reuse
IP and Reuse (PDF)
pp. null
Jürgen Haase , SICAN GmbH
pp. 728
11D: Special Session—Large European Programs in Microelectronic System and Circuit Design
pp. null
11E: Speakers
11F: Sequential Circuit Test Generation
Jaan Raik , Tallinn Technical University
Raimund Ubar , Tallinn Technical University
pp. 736
M. Konijnenburg , Delft University of Technology
J. Van der Linden , Delft University of Technology
A. van de Goor , Delft University of Technology
pp. 741
Matthew Merten , University of Illinois
Elizabeth M. Rudnick , University of Illinois
Miron Abramovici , Bell Labs - Lucent Technologies
pp. 747
Posters
A. Maamar , The University of Newcastle upon Tyne
G. Russell , The University of Newcastle upon Tyne
pp. 770
Chris Papachristou , Case Western Reserve University
Yusuf Alzazeri , Case Western Reserve University
pp. 774
Jung Hyun Choi , Federal University of Rio Grande do Sul - UFRGS
pp. 776
W. Fornaciari , Politecnico di Milano
C. Alippi , Politecnico di Milano
M. Sami , Politecnico di Milano
pp. 778
Jue Wu , Sun Microsystems
Gary S. Greenstein , Synopsys, Inc.
Elizabeth M. Rudnick , University of Illinois
pp. 780
Charles Dawson , Cadence Design Systems, Inc.
Debra Corlette , Cadence Design Systems, Inc.
Françoise Martinolle , Cadence Design Systems, Inc.
pp. 788
pp. 795
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