- D
- DATE
- 1999
- Design, Automation and Test in Europe (DATE '99)
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| | | | Bibliographic References | | | |
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Design, Automation and Test in Europe (DATE '99) Munich, Germany March 09-March 12 ISBN: 0-7695-0078-1 Table of Contents
 | Embedded System Design — The European Technology Driver |
| 1A: Verification of Sequential Circuits |
Verification of Secuential Circuits
| 1B: Architectural Issues in Low Power Design |
Architectural Issues in Low Power Design
| 1C: Design Reuse Repository and IP Architecture |
Design Reuse Repository and IP Architecture
| 2A: High Level Verification |
Stefan Höreth, Siemens Corporate R&D and Darmstadt University of Technology pp. 52
| 2B: System-Level Power Optimization |
System-Level Power Optimization
Qing Wu, University of Southern California pp. 72
| 2C: Reconfigurability and Other Issues in Embedded System Design |
Reconfigurability and Other Issues in Embedded System Design
| 2E: Embedded Core Test Approaches |
Embedded Core Test Approaches
D. Nikolos, University of Patras and Computer Technology Institute
H. T. Vergos, University of Patras and Computer Technology Institute pp. 112
A. Paschalis, Institute of Informatics & Telecommunications, NCSR "Demokritos"
N. Kranitis, Institute of Informatics & Telecommunications, NCSR "Demokritos"
M. Psarakis, Institute of Informatics & Telecommunications, NCSR "Demokritos" pp. 117
| 3A: Use of Combinational Verification |
Use of Combinational Verification
| 3B: Gate Level Power Estimation and Optimization |
Gate Level Power Estimation and Optimization
Ki-Wook Kim, University of Illinois at Urbana-Champaign pp. 158
| 3C: Special Session — Virtual Socket Interface Alliance |
Ralf Seepold, Forschungszentrum Informatik an der Universit?t Karlsruhe (FZI) pp. 182
| 3D: Speakers |
VSI Builds Momentum to Solve Design Reuse Imperative
The VSI System-Level Perspective on the Mix and Match of Virtual Components
Introduction to Virtual Component Interface
| 3E: Fault Diagnosis Techniques for Analogue Circuits |
Fault Diagnosis Techniques for Analogue Circuits
| 4A: Resource Sharing in Architectural Synthesis |
Resource Sharing in Architectural Synthesis
| 4B: Mixed Signal Characterization and Test |
Mixed Signal Characterization Test
| 4C: System Design Methodologies: Modelling, Analysis, Refinement and Synthesis |
System Design Methodologies: Modelling, Analysis, Refinement and Synthesis
| 4E: High Level Test Synthesis |
High Level Test Synthesis
| 5A: High-Level System Simulation |
High-Level System Simulation
| 5B: Analogue Circuit Sizing and Synthesis |
Analogue Circuit Sizing and Synthesis
R. Schwencker, Institute of Electronic Design Automation and Technical University of Munich
H. Graeb, Institute of Electronic Design Automation pp. 323
| 5C: VHDL-AMS and HDL Interoperability |
VHDL-AMS and HDL Interoperability
| 5E: Transistor Level Test |
| 6A: Hot Topic — Hardware Synthesis from C/C++ Models |
| 6B: Analogue Modelling and Simulation |
Analogue Modelling and Simulation
Mike Chou, Massachusetts Institute of Technology pp. 396
O. Guerra, Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
E. Roca, Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica
F. V. Fernández, Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica pp. 412
| 6C: Hot Topic — Chip Package Co-Design |
| 6E: Panel |
Scaling Towards Nanometer Technologies: Design for Test Challenges
| 7A: Functional Verification |
| 7B: Bit-Level Logic and Analogue Simulation |
Bit-Level Logic and Analogue Simulation
| 7E: Partial and Boundary Scan Test |
Partial and Boundary Scan Test
| 8A: New Languages for System Specification and Design |
New Languages for System Specification and Design
| 8B: Circuit Analysis and Design |
Circuit Analysis and Design
Heiko Holzheuer, C-LAB, Cooperation of Universit?t-GH Paderborn and Siemens AG pp. 498
A. Nunez, University of Las Palmas de Gran Canaria pp. 509
| 8C: Logic Synthesis |
| 8E: IDDX Testing and Defect Modelling |
IDDX Testing and Defect Modelling
| 9A: HW/SW Interface Synthesis and Partitioning |
HW/SW Interface Synthesis and Partitioning
| 9B: Physical Design Issues |
| 9C: Reliability and Symmetry in Architectural Synthesis |
Reliability and Symmetry in Architectural Synthesis
B. Mesman, Eindhoven University of Technology and Philips Research Laboratories pp. 602
| 9D: Panel — Single Chip or Hybrid System Integration? |
| 9E: Testing Regular Structures and Delay Faults |
Testing Regular Structures and Delay Faults
| 10A: Retiming |
| 10B: Modelling of Interconnects |
Modelling of Interconnects
| 10C: Design Reuse Methodologies for Virtual Components and IP |
Design Reuse Methodologies for Virtual Components and IP
| 10D: Embedded Tutorial — Multilanguage System Design |
Embedded Tutorial—Multilanguage System Design
| 10E: RAM BIST |
| 11B: Panel — Java, VHDL-AMS, Ada or C for System Level Specifications? |
| 11C: Hot Topic — IP and Reuse |
| 11D: Special Session—Large European Programs in Microelectronic System and Circuit Design |
| 11E: Speakers |
MEDEA—The Microelectronic Development Program for European Applications—Status of the Design-Oriented Program and Future Plan
Electronic Systems Design in the IST Program
ITEA—Information Technology and European Advancement
| 11F: Sequential Circuit Test Generation |
Sequential Circuit Test Generation
| Posters |
A. Maamar, The University of Newcastle upon Tyne pp. 770
Sergio Bampi, Federal University of Rio Grande do Sul - UFRGS pp. 776 Usage of this product signifies your acceptance of the Terms of Use.
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