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Design, Automation & Test in Europe Conference & Exhibition (1998)
Paris, France
Feb. 23, 1998 to Feb. 26, 1998
ISBN: 0-8186-8359-7
TABLE OF CONTENTS
pp. xxii
pp. xxvi
Tutorials (PDF)
pp. xxx
pp. xxxiii
Session 1A: Design Optimization of Building Blocks
Kimihiro Ogawa , Sony, Custom DA Section
Michinari Kohno , Sony, Custom DA Section
Fusako Kitamura , Sony, Custom DA Section
pp. 15
Session 1B: HW/SW Partitioning and Communication Synthesis
Peter V. Knudsen , Technical University of Denmark
Jesper Grode , Technical University of Denmark
pp. 22
M. Glesner , Darmstadt University of Technology
M. Gasteier , Darmstadt University of Technology
pp. 36
Session 1C: Asynchronous and Hybrid VHDL-Based Design
Stephen B. Furber , University of Manchester
Wen-Fang Yen , National Taipei University of Technology
pp. 44
Christoph Grimm , Goethe-University Frankfurt
Klaus Waldschmidt , Goethe-University Frankfurt
pp. 52
Session 1D: Data Path and FPGA Testing
Ishwar Parulkar , University of Southern California
Melvin A. Breuer , University of Southern California
pp. 66
Session 2A: Design Methods for High Performance Applications
Pierre Plaza , Telefonica Investigacion y Desarrollo, Madrid
Juan Carlos Diaz , Telefonica Investigacion y Desarrollo, Madrid
pp. 96
C. J. Jimenez , Instituto de Microelectronica de Sevilla.
D. R. Lopez , Instituto de Microelectronica de Sevilla.
S. Sanchez-Solano , Instituto de Microelectronica de Sevilla.
A. Barriga , Instituto de Microelectronica de Sevilla.
pp. 102
W. Eppler , Forschungszentrum Karlsruhe (FZK)
T. Fischer , Forschungszentrum Karlsruhe (FZK)
H. Gemmeke , Forschungszentrum Karlsruhe (FZK)
A. Menchikov , Joint Institute for Nuclear Research (JINR)
pp. 108
Session 2B: Scheduling in Embedded Systems
Jeroen A.J. Leijten , Philips Research Laboratories
Jef L. Van Meerbergen , Philips Research Laboratories
Adwin H. Timmer , Philips Research Laboratories
Jochen A.G. Jess , Philips Research Laboratories
pp. 125
Session 2C: Advanced Techniques for VHDL Design
Yee-Wing Hsieh , University of Pittsburgh
Steven P. Levitan , University of Pittsburgh
pp. 140
Jason Coppens , Royal Military College of Canada
Dhamin Al-Khalili , Royal Military College of Canada
Come Rozon , Royal Military College of Canada
pp. 148
Matthias Mutz , SICAN Braunschweig GmbH, Digital IC Center
pp. 153
Edwin Naroska , University of Dortmund
pp. 159
Session 2D: Novel BIST Approaches
Wei Zhao , Rockwell Semiconductor Systems Computer Engineering Department
Chris Papachristou , Rockwell Semiconductor Systems Computer Engineering Department
pp. 166
V. N. Yarmolik , Belarussian State University of Informatics and Radioelectronics
S. Hellebrand , University of Stuttgart
H.-J. Wunderlich , University of Stuttgart
pp. 173
M. Gössel , Universit?t Potsdam
H. Jürgensen , The University of Western Ontario
Y. Zorian , Logic Vision Inc.
pp. 180
Session 3A: Architectures for Image Processing
Martin Kayss , Siemens Corporate Technology
Thomas Hollstein , Darmstadt University of Technology
Claus Schneider , Siemens Corporate Technology
pp. 186
T.C.B. Yu , University of Reading
H. Cheung , Edith Cowan University
A.M. Rassau , University of Reading
K. Eshrahian , Edith Cowan University
W.A. Crossland , University of Cambridge
T.D. Wilkinson , University of Cambridge
pp. 191
Jose I. Artigas , University of Zaragoza
Jose I. Garcia , University of Zaragoza
Luis A. Barragan , University of Zaragoza
Isidro Urriza , University of Zaragoza
pp. 196
Session 3B: Scheduling and Analysis of HW/SW Systems
J.A. Maestro , Universidad Complutense - 28040 Madrid, Spain
D. Mozos , Universidad Complutense - 28040 Madrid, Spain
H. Mecha , Universidad Complutense - 28040 Madrid, Spain
pp. 218
Session 3C: Extensions to VHDL
pp. null
Guido Schumacher , Carl von Ossietzky University Oldenburg
Wolfgang Nebel , Carl von Ossietzky University Oldenburg
pp. 234
Martin Radetzki , OFFIS Research Institut, Germany
Wolfgang Nebel , OFFIS Research Institut, Germany
pp. 242
Klaus Schneider , Universit? at Karlsruhe
Ralf Reetz , Verysys GmbH
pp. 257
Session 3D: Error Detection and Design Validation
Anna Antola , Politecnico di Milano
Mariagiovanna Sami , Politecnico di Milano
pp. 266
Li-C. Wang , Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas
Jing Zeng , Somerset PowerPC Design Center, IBM, Austin, Texas
pp. 273
Kwang-Ting Cheng , University of California, Santa Barbara, CA
Malgorzata Marek-Sadowska , University of California, Santa Barbara, CA
Douglas Chang , University of California, Santa Barbara, CA
pp. 278
Session 3E: Hot Topic: IP Based System-on-a-Chip Design
Hot Topic (PDF)
pp. null
Grant Martin , Cadence Design Systems, Alta Business Unit
pp. 286
Session 4A: Design Reuse Methodologies
Dieter Garte , Fraunhofer-Institut f?r Integrierte Schaltungen, EAS Dresden
Manfred Koegst , Fraunhofer-Institut f?r Integrierte Schaltungen, EAS Dresden
Michael Wahl , Universit?t-GH Siegen
pp. 292
Jörg Böttger , Chemnitz University of Technology
Karlheinz Agsteiner , Chemnitz University of Technology
Dieter Monjau , Chemnitz University of Technology
Sören Schulze , Chemnitz University of Technology
pp. 303
Session 4B: Flat and Timing-Driven Processor Design
Ulrich Baur , IBM Entwicklung GmbH Boeblingen
Thomas Ludwig , IBM Entwicklung GmbH Boeblingen
Bernhard Kick , IBM Entwicklung GmbH Boeblingen
Juergen Koehl , IBM Entwicklung GmbH Boeblingen
pp. 312
Jens Vygen , University of Bonn
pp. 321
Uwe Fassnacht , IBM Entwicklung GmbH Boeblingen
Juergen Schietke , University of Bonn
pp. 325
Asmus Hetzel , University of Bonn
pp. 332
Session 4C: Hot Topic: Reconfigurable Systems
Jan Rabaey , University of California, Berkeley
Marlene Wan , University of California, Berkeley
pp. 341
Ian Page , Oxford University Computing Lab
pp. 343
Session 4D: Digital Simulation and Estimation
V. Chandramouli , EECS Department, The University of Michigan,
Jesse P. Whittemore , EECS Department, The University of Michigan,
Karem A. Sakallah , EECS Department, The University of Michigan,
pp. 350
St. Schmerler , Electronic Systems and Microsystems (ESM)
K.D. Miiller-Glaser , Electronic Systems and Microsystems (ESM)
pp. 362
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Marino T.J. Strik , Philips Research laboratories
Adwin H. Timmer , Philips Research laboratories
Bart Mesman , Philips Research laboratories
Jochen A.G. Jess , Eindhoven University of Technology
pp. 377
Ju-Hwan Yi , Korea Advanced Institute of Science and Technology
Hoon Choi , Korea Advanced Institute of Science and Technology
In-Cheol Park , Korea Advanced Institute of Science and Technology
Seung Ho Hwang , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology
pp. 384
Session 5B: Partitioning and Routing
Jianjian Song , National University of Singapore
Zhaoxuan Shen , National University of Singapore
Wenjun Zhuang , National University of Singapore
pp. 398
Gabriel Robins , University of Virginia, Charlottesville
C. S. Helvig , University of Virginia, Charlottesville
pp. 406
Thorsten Adler , University of Hanover
Juergen Schaeuble , Robert Bosch GmbH
pp. 414
Session 5C: Panel - Formal Verification: A New Standard CAD Tool for the Industrial Design Flow
Panel (PDF)
pp. null
Session 5D: Simulation for High-Level Design
Andrea Mueller , RWTH Aachen, University of Technology
Guido Post , RWTH Aachen, University of Technology
pp. 424
Markus Willems , Aachen University of Technology
Martin Coors , Aachen University of Technology
Holger Keding , Aachen University of Technology
pp. 429
Arno Kunzmann , Universit?t T?bingen
Cordula Hansen , Universit?t T?bingen
pp. 436
Session 6A: Architectural Synthesis
Min Xu , University of California, Irvine
pp. 446
Oliver Bringmann , Forschungszentrum Informatik
Wolfgang Rosenstiel , Universitaet Tuebingen
pp. 451
Jian Li , University of Illinois at Urbana-Champaign
pp. 457
Session 6B: Timing and Crosstalk in Interconnect
Sudhakar Muddu , Silicon Graphics, Inc.
Andrew B. Kahng , Silicon Graphics, Inc.
Rahul Sharma , Silicon Graphics, Inc.
pp. 471
Session 6C: Panel: Next Generation System Design Tools
Panel (PDF)
pp. null
Session 6D: IDDQ and Memory Testing
R. Rodriguez-Montanes , Universitat Politecnica de Catalunya
J. Figueras , Universitat Politecnica de Catalunya
pp. 490
A.J. van de Goor , Delft University of Technology
pp. 501
Session 7A: Microsystems
Microsystems (PDF)
pp. null
U. Becker , Robert Bosch GmbH FhG-IIS/EAS
G. Lorenz P. Schwarz , Robert Bosch GmbH FhG-IIS/EAS
R. Neul , Robert Bosch GmbH FhG-IIS/EAS
pp. 510
V. Szekely , Technical University of Budapest, Dept. of Electron Devices
pp. 518
Marcelo Lubaszewski , DELET/UFRGS
Erika F. Cota , DELET/UFRGS
Bernard Courtois , TIMA Laboratory
pp. 524
Session 7B: Interconnect Modeling
Roland W. Freund , Bell Laboratories, Lucent Technologies
Peter Feldmann , Bell Laboratories, Lucent Technologies
pp. 530
Mattan Kamon , Massachusetts Institute of Technology
Jacob White , Massachusetts Institute of Technology
Nuno Marques , INESC
pp. 538
Jianhua Shao , City University of Hong Kong
Richard M.M. Chen , City University of Hong Kong
pp. 544
Session 7C: Design for Manufacturability - Embedded Tutorial
P.K. Nag , Carnegie Mellon University
Wojciech Maly , Carnegie Mellon University
J. Khare , Level One Communications
pp. 550
P.K. Nag , Carnegie Mellon University
C. Ouyang , Carnegie Mellon University
H.T. Heineken , Level One Communications
J. Khare , Level One Communications
P. Simon , Philips NV, Nijmegen, The Netherlands
pp. 557
Hans T. Heineken , Level One Communications
Wojciech Maly , Carnegie Mellon University
pp. 563
Session 7D: Sequential Circuit Testing
Session 8A: Issues in Behavioral Synthesis
A. Jemai , INSAT, Tunis, Tunisia
P. Kission , ANACAD, Grenoble France
A.A. Jerraya , TIMA Laboratory, Grenoble, France
pp. 590
Ahmed Hemani , Royal Institute of Technology (KTH)
Anshul Kumar , Indian Institute of Technology
pp. 596
Session 8B: Formal Equivalence Checking Using Decision Diagrams
Stefan Horeth , Darmstadt University of Technology
pp. 612
C.A.J. Van Eijk , Eindhoven University of Technology
pp. 618
Lluis Ribas , Autonomous University of Barcelona (UAB)
Jordi Carrabina , Autonomous University of Barcelona (UAB)
pp. 624
Session 8C: Hot Topic: Silicon Debug of Systems-on-Chips
Hot Topic (PDF)
pp. null
Session 8D: Characterization and Verification of Analogue Circuits
Josef Eckmueller , Siemens AG, Munich
Martin Groepl , Siemens AG, Munich
Helmut E. Graeb , Techn. Univ. Munich
pp. 636
G. Droege , SICAN
M. Thole , Institut fuer Netzwerktheorie und Schaltungstechnik
E.-H. Horneber , Institut fuer Netzwerktheorie und Schaltungstechnik
pp. 644
Session 9A: Benchmark Circuits, Technology Mapping and Scan Chains
Nevin Kapur , CBL (Collaborative Benchmarking Laboratory)
Debabrata Ghosh , CBL (Collaborative Benchmarking Laboratory)
Justin Harlow III , National Semiconductor Corporation, Santa Clara
pp. 656
Guenter Stenz , Technical University of Munich
Aiguo Lu , Technical University of Munich
pp. 664
Paolo Prinetto , Politecnico di Torino
Fulvio Corno , Politecnico di Torino
Massimo Violante , Politecnico di Torino
pp. 670
Session 9B: Physical to Gate Level Design for Low-Power
J.M. Daga , LIRMM, UMR CNRS
E. Ottaviano , LIRMM, UMR CNRS
D. Auvergne , LIRMM, UMR CNRS
pp. 680
Qi Wang , University of Arizona
Sarma B.K. Vrudhula , University of Arizona
pp. 686
Jaewon Oh , University of Southern California
pp. 692
Yi-Min Jiang , University of California, Santa Barbara, CA
Kwang-Ting Cheng , University of California, Santa Barbara, CA
pp. 698
Session 9C: Hot Topic: Embedded Memory and Embedded Logic
Hot Topic (PDF)
pp. null
Norbert Wehn , University of Kaiserslautern
pp. 704
Session 9D: Analogue Circuit Modeling and Design Methodology
R. Rosenberger , Darmstadt University of Technology
S. A. Huss , Darmstadt University of Technology
pp. 721
O. Koufopavlou , University of Patras
C. Goutis , University of Patras
S. Nikolaidis , Aristotle University of Thessaloniki
pp. 729
Session 10A: Combinational Logical Synthesis
J.W.J.M. Rutten , Eindhoven University of Technology
M.R.C.M. Berkelaar , Eindhoven University of Technology
C.A.J. Van Eijk , Eindhoven University of Technology
M.A.J. Kolsteren , Eindhoven University of Technology
pp. 749
Hiroshi Sawada , NTT Communication Science Laboratories
Shigeru Yamashitam , NTT Communication Science Laboratories
Akira Nagoya , NTT Communication Science Laboratories
pp. 755
Session 10B: High Level Power Estimation
Franco Fummi , Politecnico di Torino, ITALY
Fabrizio Ferrandi , Politecnico di Torino, ITALY
Massimo Poncino , Politecnico di Torino, ITALY
pp. 762
Alessandro Bogliolo , DEIS - University of Bologna
Giovanni de Micheli , CSL - Stanford University
pp. 767
Radu Marculescu , University of Southern California, Los Angeles, CA 90089
Diana Marculescu , University of Southern California, Los Angeles, CA 90089
pp. 774
Session 10C: Petri Nets and Dedicated Formalisms
Gjalt de Jong , Alcatel Telecom
Bill Lin , University of California, San Diego
pp. 782
Enric Pastor , Universitat Polit`ecnica de Catalunya
Jordi Cortadella , Universitat Polit`ecnica de Catalunya
pp. 790
Maroun Kassab , Universite de Montreal
Eduard Cerny , Universite de Montreal
Sidi Aourid , Universite de Montreal
Thomas Krodel , Nortel
pp. 796
Evguenii I. Goldberg , Cadence Berkeley Laboratories
Yuji Kukimoto , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 803
Session 10D: Mixed-Signal Test and DFT
Salvador Mir , Universidad de Sevilla
Adoracion Rueda , Universidad de Sevilla
Diego Vazquez , Universidad de Sevilla
Jose Luis Huertas , Universidad de Sevilla
pp. 810
Walter M. Lindermeir , Technical University of Munich
Helmut E. Graeb , Technical University of Munich
pp. 822
Session 11A: Sequential Logic Synthesis
Maria J. Avedillo , Instituto de Microelectronica de Sevilla
Jose M. Quintana , Instituto de Microelectronica de Sevilla
Manuel Martinez , Instituto de Microelectronica de Sevilla
pp. 835
Naresh Maheshwari , Iowa State University, Ames IA
pp. 840
Session 11B: High-Level Power Optimization
Kamal S. Khouri , Princeton University, Princeton, NJ 08544
Niraj K. Jha , Princeton University, Princeton, NJ 08544
pp. 848
Tohru Ishihara , Kyushu University
Hiroyuki Tomiyama , Kyushu University
Hiroto Yasuura , Kyushu University
pp. 855
Giovanni de Micheli , Stanford University
Donatella Sciuto , Politecnico di Milano
Enrico Macii , Automatica e Informatica, Torino, Italy
Luca Benini , Stanford University
pp. 861
Session 11C: System Architecture Design
Michael Mrva , Siemens AG, Corporate Technology, ZT ME 5
Klaus Buchenrieder , Siemens AG, Corporate Technology, ZT ME 5
Rainer Kress , Siemens AG, Corporate Technology, ZT ME 5
pp. 868
Valentina Salapura , Technische Universitaet Wien
pp. 875
Session 11D: Simulation and Test Tools for Analogue Circuits
Mike Chou , Massachusetts Institute of Technology
L. Miguel Silveira , INESC/Cadence European Laboratories
pp. 892
Michael W. Tian , University of Iowa, Iowa City
C.-J. Richard Shi , University of Iowa, Iowa City
pp. 899
Poster Session
R. Niemann , University of Dortmund
P. Marwedel , University of Dortmund
pp. 912
Tom Kazmierski , University of Southampton
pp. 916
M.L. Flottes , Micro?lectronique de Montpellier,U.M. CNRS 9928
R. Pires , Micro?lectronique de Montpellier,U.M. CNRS 9928
B. Rouzeyre , Micro?lectronique de Montpellier,U.M. CNRS 9928
L. Volpe , Micro?lectronique de Montpellier,U.M. CNRS 9928
pp. 921
Davor Runje , University of Zagreb
pp. 923
Nikil D. Dutt , University of California, Irvine
Alexandru Nicolau , University of California, Irvine
pp. 925
D. Heller , IRESTE, University of NANTES, FRANCE
F. Muller , IRESTE, University of NANTES, FRANCE
J.P. Calvez , IRESTE, University of NANTES, FRANCE
pp. 927
Anupam Basu , University of Dortmund, Germany
Rainer Leupers , University of Dortmund, Germany
Peter Marwedel , University of Dortmund, Germany
pp. 929
Thomas Mueller-Wipperfuerth , Johannes Kepler University Linz, Austria
Richard Hagelauer , Johannes Kepler University Linz, Austria
pp. 931
George Economakos , National Technical University of Athens
George Papakonstantinou , National Technical University of Athens
Panayotis Tsanakas , National Technical University of Athens
pp. 933
Hans-Georg Martin , University of T?bingen
pp. 939
Tom J. Kazmierski (Abstract)
pp. 941
Wonyong Sung , Seoul National University
Soonhoi Ha , Seoul National University
pp. 945
V. de Armas , University of Las Palmas de Gran Canaria
R. Sarmiento , University of Las Palmas de Gran Canaria
A. Nunez , University of Las Palmas de Gran Canaria
pp. 947
Chih-Tung Chen , Unified Design System Laboratory
Kayhan Kucukcakar , Unified Design System Laboratory
pp. 949
Hideaki Kimura , NTT Access Network Systems Laboratories
Norihito Iyenaga , NTT Access Network Systems Laboratories
pp. 951
Y. Torroja , Universidad Politecnica de Madrid
E. de la Torre , Universidad Politecnica de Madrid
T. Riesgo , Universidad Politecnica de Madrid
pp. 955
Cristiana Bolchini , Dipartimento di Elettronica e Informazione
Fabio Salice , Dipartimento di Elettronica e Informazione
Donatella Sciuto , Dipartimento di Elettronica e Informazione
pp. 957
M. Svajda , Technical University of Brno
B. Straka , CEDO, Brno
H. Manhaeve , KHBO, Microelectronics Department, Oostende, Belgium
pp. 959
M. Wolf , Otto-von-Guericke-University of Magdeburg
pp. 961
Anatoly Prihozhy , State University of Informatics and Radioelectronics of Belarus
pp. 963
Thomas Lindenkreuz , Robert Bosch GmbH
Matthias Ringe , Robert Bosch GmbH
pp. 965
Bogdan G. Arsintescu , Delft University of Technology
pp. 971
Irith Pomeranz , University of Iowa
pp. 973
Felix Nicoli , Universite de Provence
pp. 975
J.M. Mendias , Universidad Complutense de Madrid
pp. 977
Satyamurthy Pullela , Monterey Design Systems, San Jose, CA
Rajendran Panda , Motorola Inc., Austin, TX
Abhijit Dharchoudhury , Motorola Inc., Austin, TX
Gopal Vija , Motorola Inc., Austin, TX
pp. 985
Th. Calin , Reliable Integrated Systems Group, TIMA/INPG
M. Nicolaidis , Reliable Integrated Systems Group, TIMA/INPG
pp. 987
Author Index (PDF)
pp. 989
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