• D
  • DATE
  • 1998
  • Design Automation and Test in Europe (DATE '98)
Advanced Search 
Design Automation and Test in Europe (DATE '98)
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
Table of Contents
Session 1A: Design Optimization of Building Blocks
Design Optimization of Building Blocks
Session 1B: HW/SW Partitioning and Communication Synthesis
HW/SW Partitioning and Communication Synthesis
Jesper Grode, Technical University of Denmark
Peter V. Knudsen, Technical University of Denmark
Jan Madsen, Technical University of Denmark
pp. 22
M. Gasteier, Darmstadt University of Technology
M. Glesner, Darmstadt University of Technology
M. Muench, University of Kaiserslautern
pp. 36
Session 1C: Asynchronous and Hybrid VHDL-Based Design
Asynchronous and Hybrid VHDL-Based Design
Sun-Yen Tan, University of Manchester
Stephen B. Furber, University of Manchester
Wen-Fang Yen, National Taipei University of Technology
pp. 44
Session 1D: Data Path and FPGA Testing
Data Path and FPGA Testing
Ishwar Parulkar, University of Southern California
Sandeep K. Gupta, University of Southern California
Melvin A. Breuer, University of Southern California
pp. 66
Session 2A: Design Methods for High Performance Applications
Design Methods for High Performance Applications
Juan Carlos Diaz, Telefonica Investigacion y Desarrollo, Madrid
Pierre Plaza, Telefonica Investigacion y Desarrollo, Madrid
Jesus Crespo, Telefonica Investigacion y Desarrollo, Madrid
pp. 96
E. Lago, Instituto de Microelectronica de Sevilla.
C. J. Jimenez, Instituto de Microelectronica de Sevilla.
D. R. Lopez, Instituto de Microelectronica de Sevilla.
S. Sanchez-Solano, Instituto de Microelectronica de Sevilla.
A. Barriga, Instituto de Microelectronica de Sevilla.
pp. 102
W. Eppler, Forschungszentrum Karlsruhe (FZK)
T. Fischer, Forschungszentrum Karlsruhe (FZK)
H. Gemmeke, Forschungszentrum Karlsruhe (FZK)
A. Menchikov, Joint Institute for Nuclear Research (JINR)
pp. 108
Session 2B: Scheduling in Embedded Systems
Scheduling in Embedded Systems
Jeroen A.J. Leijten, Philips Research Laboratories
Jef L. Van Meerbergen, Philips Research Laboratories
Adwin H. Timmer, Philips Research Laboratories
Jochen A.G. Jess, Philips Research Laboratories
pp. 125
Session 2C: Advanced Techniques for VHDL Design
Advanced Techniques for VHDL Design
Jason Coppens, Royal Military College of Canada
Dhamin Al-Khalili, Royal Military College of Canada
Come Rozon, Royal Military College of Canada
pp. 148
Session 2D: Novel BIST Approaches
Novel BIST Approaches
Wei Zhao, Rockwell Semiconductor Systems Computer Engineering Department
Chris Papachristou, Rockwell Semiconductor Systems Computer Engineering Department
pp. 166
V. N. Yarmolik, Belarussian State University of Informatics and Radioelectronics
S. Hellebrand, University of Stuttgart
H.-J. Wunderlich, University of Stuttgart
pp. 173
T. Bogue, University of Waterloo
M. Gössel, Universit?t Potsdam
H. Jürgensen, The University of Western Ontario
Y. Zorian, Logic Vision Inc.
pp. 180
Session 3A: Architectures for Image Processing
Architectures for Image Processing
Claus Schneider, Siemens Corporate Technology
Martin Kayss, Siemens Corporate Technology
Thomas Hollstein, Darmstadt University of Technology
Juergen Deicke, Darmstadt University of Technology
pp. 186
A.M. Rassau, University of Reading
T.C.B. Yu, University of Reading
H. Cheung, Edith Cowan University
S.W. Lachowicz, Edith Cowan University
K. Eshrahian, Edith Cowan University
W.A. Crossland, University of Cambridge
T.D. Wilkinson, University of Cambridge
pp. 191
Session 3B: Scheduling and Analysis of HW/SW Systems
Scheduling and Analysis of HW/SW Systems
J.A. Maestro, Universidad Complutense - 28040 Madrid, Spain
D. Mozos, Universidad Complutense - 28040 Madrid, Spain
H. Mecha, Universidad Complutense - 28040 Madrid, Spain
pp. 218
Session 3C: Extensions to VHDL
Extensions to VHDL
Guido Schumacher, Carl von Ossietzky University Oldenburg
Wolfgang Nebel, Carl von Ossietzky University Oldenburg
pp. 234
Wolfram Putzke-Röming, OFFIS Research Institut, Germany
Martin Radetzki, OFFIS Research Institut, Germany
Wolfgang Nebel, OFFIS Research Institut, Germany
pp. 242
Session 3D: Error Detection and Design Validation
Error Detection and Design Validation
Li-C. Wang, Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas
Magdy S. Abadir, Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas
Jing Zeng, Somerset PowerPC Design Center, IBM, Austin, Texas
pp. 273
Douglas Chang, University of California, Santa Barbara, CA
Kwang-Ting Cheng, University of California, Santa Barbara, CA
Malgorzata Marek-Sadowska, University of California, Santa Barbara, CA
Mike Tien-Chien Lee, Avant! Corp.
pp. 278
Session 3E: Hot Topic: IP Based System-on-a-Chip Design
Hot Topic
Session 4A: Design Reuse Methodologies
Design Reuse Methodologies
Manfred Koegst, Fraunhofer-Institut f?r Integrierte Schaltungen, EAS Dresden
Dieter Garte, Fraunhofer-Institut f?r Integrierte Schaltungen, EAS Dresden
Peter Conradi, Universit?t-GH Siegen
Michael Wahl, Universit?t-GH Siegen
pp. 292
Jörg Böttger, Chemnitz University of Technology
Karlheinz Agsteiner, Chemnitz University of Technology
Dieter Monjau, Chemnitz University of Technology
Sören Schulze, Chemnitz University of Technology
pp. 303
Session 4B: Flat and Timing-Driven Processor Design
Flat and Timing-Driven Processor Design
Juergen Koehl, IBM Entwicklung GmbH Boeblingen
Ulrich Baur, IBM Entwicklung GmbH Boeblingen
Thomas Ludwig, IBM Entwicklung GmbH Boeblingen
Bernhard Kick, IBM Entwicklung GmbH Boeblingen
Thomas Pflueger, IBM Entwicklung GmbH Boeblingen
pp. 312
Session 4C: Hot Topic: Reconfigurable Systems
Hot Topic: Reconfigurable Systems
Jan Rabaey, University of California, Berkeley
Marlene Wan, University of California, Berkeley
pp. 341
Session 4D: Digital Simulation and Estimation
Digital Simulation and Estimation
V. Chandramouli, EECS Department, The University of Michigan,
Jesse P. Whittemore, EECS Department, The University of Michigan,
Karem A. Sakallah, EECS Department, The University of Michigan,
pp. 350
St. Schmerler, Electronic Systems and Microsystems (ESM)
Y. Tanurhan, Electronic Systems and Microsystems (ESM)
K.D. Miiller-Glaser, Electronic Systems and Microsystems (ESM)
pp. 362
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Synthesis of Reprogrammable and Reconfigurable Architectures
Bart Mesman, Philips Research laboratories
Marino T.J. Strik, Philips Research laboratories
Adwin H. Timmer, Philips Research laboratories
Jef L. Van Meerbergen, Philips Research laboratories
Jochen A.G. Jess, Eindhoven University of Technology
pp. 377
Ju-Hwan Yi, Korea Advanced Institute of Science and Technology
Hoon Choi, Korea Advanced Institute of Science and Technology
In-Cheol Park, Korea Advanced Institute of Science and Technology
Seung Ho Hwang, Korea Advanced Institute of Science and Technology
Chong-Min Kyung, Korea Advanced Institute of Science and Technology
pp. 384
Session 5B: Partitioning and Routing
Partitioning and Routing
Jianjian Song, National University of Singapore
Zhaoxuan Shen, National University of Singapore
Wenjun Zhuang, National University of Singapore
pp. 398
C. S. Helvig, University of Virginia, Charlottesville
Gabriel Robins, University of Virginia, Charlottesville
Alexander Zelikovsky, University of Virginia, Charlottesville
pp. 406
Session 5C: Panel - Formal Verification: A New Standard CAD Tool for the Industrial Design Flow
Panel
Session 5D: Simulation for High-Level Design
Simulation for High-Level Design
Guido Post, RWTH Aachen, University of Technology
Andrea Mueller, RWTH Aachen, University of Technology
Thorsten Groetker, RWTH Aachen, University of Technology
pp. 424
Holger Keding, Aachen University of Technology
Markus Willems, Aachen University of Technology
Martin Coors, Aachen University of Technology
Heinrich Meyr, Aachen University of Technology
pp. 429
Session 6A: Architectural Synthesis
Architectural Synthesis
Min Xu, University of California, Irvine
Fadi J. Kurdahi, University of California, Irvine
pp. 446
Session 6B: Timing and Crosstalk in Interconnect
Timing and Crosstalk in Interconnect
Andrew B. Kahng, Silicon Graphics, Inc.
Sudhakar Muddu, Silicon Graphics, Inc.
Egino Sarto, Silicon Graphics, Inc.
Rahul Sharma, Silicon Graphics, Inc.
pp. 471
Session 6C: Panel: Next Generation System Design Tools
Panel
Session 6D: IDDQ and Memory Testing
IDDQ and Memory Testing
A.J. van de Goor, Delft University of Technology
I.B.S. Tlili, Delft University of Technology
pp. 501
Session 7A: Microsystems
Microsystems
R. Neul, Robert Bosch GmbH FhG-IIS/EAS
U. Becker, Robert Bosch GmbH FhG-IIS/EAS
G. Lorenz P. Schwarz, Robert Bosch GmbH FhG-IIS/EAS
J. Haase S. Wünsche, Robert Bosch GmbH FhG-IIS/EAS
pp. 510
V. Szekely, Technical University of Budapest, Dept. of Electron Devices
M. Rencz, Technical University of Budapest, Dept. of Electron Devices
pp. 518
Session 7B: Interconnect Modeling
Interconnect Modeling
Nuno Marques, INESC
Mattan Kamon, Massachusetts Institute of Technology
Jacob White, Massachusetts Institute of Technology
L. Miguel Silveira, INESC/Cadence European Laboratories
pp. 538
Session 7C: Design for Manufacturability - Embedded Tutorial
Design for Manufacturability - Embedded Tutorial
Wojciech Maly, Carnegie Mellon University
P.K. Nag, Carnegie Mellon University
Hans T. Heineken, Level One Communications
J. Khare, Level One Communications
pp. 550
W. Maly, Carnegie Mellon University
P.K. Nag, Carnegie Mellon University
C. Ouyang, Carnegie Mellon University
H.T. Heineken, Level One Communications
J. Khare, Level One Communications
P. Simon, Philips NV, Nijmegen, The Netherlands
pp. 557
Session 7D: Sequential Circuit Testing
Sequential Circuit Testing
Session 8A: Issues in Behavioral Synthesis
Issues in Behavioral Synthesis
A. Jemai, INSAT, Tunis, Tunisia
P. Kission, ANACAD, Grenoble France
A.A. Jerraya, TIMA Laboratory, Grenoble, France
pp. 590
Johnny Öberg, Royal Institute of Technology (KTH)
Ahmed Hemani, Royal Institute of Technology (KTH)
Anshul Kumar, Indian Institute of Technology
pp. 596
Session 8B: Formal Equivalence Checking Using Decision Diagrams
Formal Equivalence Checking Using Decision Diagrams
Session 8C: Hot Topic: Silicon Debug of Systems-on-Chips
Hot Topic
Session 8D: Characterization and Verification of Analogue Circuits
Characterization and Verification of Analogue Circuits
G. Droege, SICAN
M. Thole, Institut fuer Netzwerktheorie und Schaltungstechnik
E.-H. Horneber, Institut fuer Netzwerktheorie und Schaltungstechnik
pp. 644
Session 9A: Benchmark Circuits, Technology Mapping and Scan Chains
Benchmark Circuits, Technology Mapping and Scan Chains
Debabrata Ghosh, CBL (Collaborative Benchmarking Laboratory)
Nevin Kapur, CBL (Collaborative Benchmarking Laboratory)
Franc Brglez, CBL (Collaborative Benchmarking Laboratory)
Justin Harlow III, National Semiconductor Corporation, Santa Clara
pp. 656
Aiguo Lu, Technical University of Munich
Guenter Stenz, Technical University of Munich
Frank M. Johannes, Technical University of Munich
pp. 664
Session 9B: Physical to Gate Level Design for Low-Power
Physical to Gate Level Design for Low-Power
Jaewon Oh, University of Southern California
Massoud Pedram, University of Southern California
pp. 692
Yi-Min Jiang, University of California, Santa Barbara, CA
Kwang-Ting Cheng, University of California, Santa Barbara, CA
pp. 698
Session 9C: Hot Topic: Embedded Memory and Embedded Logic
Hot Topic
Session 9D: Analogue Circuit Modeling and Design Methodology
Analogue Circuit Modeling and Design Methodology
L. Bisdounis, University of Patras
O. Koufopavlou, University of Patras
C. Goutis, University of Patras
S. Nikolaidis, Aristotle University of Thessaloniki
pp. 729
Session 10A: Combinational Logical Synthesis
Combinational Logical Synthesis
J.W.J.M. Rutten, Eindhoven University of Technology
M.R.C.M. Berkelaar, Eindhoven University of Technology
C.A.J. Van Eijk, Eindhoven University of Technology
M.A.J. Kolsteren, Eindhoven University of Technology
pp. 749
Hiroshi Sawada, NTT Communication Science Laboratories
Shigeru Yamashitam, NTT Communication Science Laboratories
Akira Nagoya, NTT Communication Science Laboratories
pp. 755
Session 10B: High Level Power Estimation
High Level Power Estimation
Fabrizio Ferrandi, Politecnico di Torino, ITALY
Franco Fummi, Politecnico di Torino, ITALY
Enrico Macii, Politecnico di Torino, ITALY
Massimo Poncino, Politecnico di Torino, ITALY
pp. 762
Alessandro Bogliolo, DEIS - University of Bologna
Luca Benini, CSL - Stanford University
Giovanni de Micheli, CSL - Stanford University
pp. 767
Diana Marculescu, University of Southern California, Los Angeles, CA 90089
Radu Marculescu, University of Southern California, Los Angeles, CA 90089
Massoud Pedram, University of Southern California, Los Angeles, CA 90089
pp. 774
Session 10C: Petri Nets and Dedicated Formalisms
Petri Nets and Dedicated Formalisms
Enric Pastor, Universitat Polit`ecnica de Catalunya
Jordi Cortadella, Universitat Polit`ecnica de Catalunya
pp. 790
Evguenii I. Goldberg, Cadence Berkeley Laboratories
Yuji Kukimoto, University of California, Berkeley
Robert K. Brayton, University of California, Berkeley
pp. 803
Session 10D: Mixed-Signal Test and DFT
Mixed-Signal Test and DFT
Salvador Mir, Universidad de Sevilla
Adoracion Rueda, Universidad de Sevilla
Diego Vazquez, Universidad de Sevilla
Jose Luis Huertas, Universidad de Sevilla
pp. 810
Session 11A: Sequential Logic Synthesis
Sequential Logic Synthesis
Manuel Martinez, Instituto de Microelectronica de Sevilla
Maria J. Avedillo, Instituto de Microelectronica de Sevilla
Jose M. Quintana, Instituto de Microelectronica de Sevilla
Jose L. Huertas, Instituto de Microelectronica de Sevilla
pp. 835
Session 11B: High-Level Power Optimization
High-Level Power Optimization
Kamal S. Khouri, Princeton University, Princeton, NJ 08544
Ganesh Lakshminarayana, Princeton University, Princeton, NJ 08544
Niraj K. Jha, Princeton University, Princeton, NJ 08544
pp. 848
Luca Benini, Stanford University
Giovanni de Micheli, Stanford University
Donatella Sciuto, Politecnico di Milano
Enrico Macii, Automatica e Informatica, Torino, Italy
Cristina Silvano, Universita` di Brescia
pp. 861
Session 11C: System Architecture Design
System Architecture Design
Michael Mrva, Siemens AG, Corporate Technology, ZT ME 5
Klaus Buchenrieder, Siemens AG, Corporate Technology, ZT ME 5
Rainer Kress, Siemens AG, Corporate Technology, ZT ME 5
pp. 868
Session 11D: Simulation and Test Tools for Analogue Circuits
Simulation and Test Tools for Analogue Circuits
Poster Session
M.L. Flottes, Micro?lectronique de Montpellier,U.M. CNRS 9928
R. Pires, Micro?lectronique de Montpellier,U.M. CNRS 9928
B. Rouzeyre, Micro?lectronique de Montpellier,U.M. CNRS 9928
L. Volpe, Micro?lectronique de Montpellier,U.M. CNRS 9928
pp. 921
Preeti Ranjan Panda, University of California, Irvine
Nikil D. Dutt, University of California, Irvine
Alexandru Nicolau, University of California, Irvine
pp. 925
J.P. Calvez, IRESTE, University of NANTES, FRANCE
D. Heller, IRESTE, University of NANTES, FRANCE
F. Muller, IRESTE, University of NANTES, FRANCE
O. Pasquier, IRESTE, University of NANTES, FRANCE
pp. 927
Anupam Basu, University of Dortmund, Germany
Rainer Leupers, University of Dortmund, Germany
Peter Marwedel, University of Dortmund, Germany
pp. 929
George Economakos, National Technical University of Athens
George Papakonstantinou, National Technical University of Athens
Panayotis Tsanakas, National Technical University of Athens
pp. 933
J. A. Montiel-Nelson, University of Las Palmas de Gran Canaria
V. de Armas, University of Las Palmas de Gran Canaria
R. Sarmiento, University of Las Palmas de Gran Canaria
A. Nunez, University of Las Palmas de Gran Canaria
pp. 947
Jie Gong, Unified Design System Laboratory
Chih-Tung Chen, Unified Design System Laboratory
Kayhan Kucukcakar, Unified Design System Laboratory
pp. 949
T. Riesgo, Universidad Politecnica de Madrid
Y. Torroja, Universidad Politecnica de Madrid
E. de la Torre, Universidad Politecnica de Madrid
J. Uceda, Universidad Politecnica de Madrid
pp. 955
Cristiana Bolchini, Dipartimento di Elettronica e Informazione
Fabio Salice, Dipartimento di Elettronica e Informazione
Donatella Sciuto, Dipartimento di Elettronica e Informazione
pp. 957
M. Svajda, Technical University of Brno
B. Straka, CEDO, Brno
H. Manhaeve, KHBO, Microelectronics Department, Oostende, Belgium
pp. 959
M. Wolf, Otto-von-Guericke-University of Magdeburg
U. Kleine, Otto-von-Guericke-University of Magdeburg
pp. 961
Anatoly Prihozhy, State University of Informatics and Radioelectronics of Belarus
pp. 963
J.M. Mendias, Universidad Complutense de Madrid
R. Hermida, Universidad Complutense de Madrid
pp. 977
Satyamurthy Pullela, Monterey Design Systems, San Jose, CA
Rajendran Panda, Motorola Inc., Austin, TX
Abhijit Dharchoudhury, Motorola Inc., Austin, TX
Gopal Vija, Motorola Inc., Austin, TX
pp. 985
J. Velasco-Medina, Reliable Integrated Systems Group, TIMA/INPG
Th. Calin, Reliable Integrated Systems Group, TIMA/INPG
M. Nicolaidis, Reliable Integrated Systems Group, TIMA/INPG
pp. 987
Usage of this product signifies your acceptance of the Terms of Use.