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- DATE
- 1998
- Design Automation and Test in Europe (DATE '98)
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Design Automation and Test in Europe (DATE '98) Paris, France February 23-February 26 ISBN: 0-8186-8359-7 Table of Contents
 | Session 1A: Design Optimization of Building Blocks |
Design Optimization of Building Blocks
| Session 1B: HW/SW Partitioning and Communication Synthesis |
HW/SW Partitioning and Communication Synthesis
| Session 1C: Asynchronous and Hybrid VHDL-Based Design |
Asynchronous and Hybrid VHDL-Based Design
| Session 1D: Data Path and FPGA Testing |
Data Path and FPGA Testing
| Session 2A: Design Methods for High Performance Applications |
Design Methods for High Performance Applications
E. Lago, Instituto de Microelectronica de Sevilla.
A. Barriga, Instituto de Microelectronica de Sevilla. pp. 102
| Session 2B: Scheduling in Embedded Systems |
Scheduling in Embedded Systems
| Session 2C: Advanced Techniques for VHDL Design |
Advanced Techniques for VHDL Design
| Session 2D: Novel BIST Approaches |
Wei Zhao, Rockwell Semiconductor Systems Computer Engineering Department pp. 166
V. N. Yarmolik, Belarussian State University of Informatics and Radioelectronics pp. 173
| Session 3A: Architectures for Image Processing |
Architectures for Image Processing
| Session 3B: Scheduling and Analysis of HW/SW Systems |
Scheduling and Analysis of HW/SW Systems
Bill Lin, University of California, San Diego pp. 211
D. Mozos, Universidad Complutense - 28040 Madrid, Spain
H. Mecha, Universidad Complutense - 28040 Madrid, Spain pp. 218
| Session 3C: Extensions to VHDL |
| Session 3D: Error Detection and Design Validation |
Error Detection and Design Validation
Li-C. Wang, Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas
Magdy S. Abadir, Somerset PowerPC Design Center, Motorola, Inc., Austin, Texas
Jing Zeng, Somerset PowerPC Design Center, IBM, Austin, Texas pp. 273
| Session 3E: Hot Topic: IP Based System-on-a-Chip Design |
| Session 4A: Design Reuse Methodologies |
Design Reuse Methodologies
Manfred Koegst, Fraunhofer-Institut f?r Integrierte Schaltungen, EAS Dresden
Dieter Garte, Fraunhofer-Institut f?r Integrierte Schaltungen, EAS Dresden pp. 292
| Session 4B: Flat and Timing-Driven Processor Design |
Flat and Timing-Driven Processor Design
| Session 4C: Hot Topic: Reconfigurable Systems |
Hot Topic: Reconfigurable Systems
Ian Page, Oxford University Computing Lab pp. 343
| Session 4D: Digital Simulation and Estimation |
Digital Simulation and Estimation
| Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures |
Synthesis of Reprogrammable and Reconfigurable Architectures
Ju-Hwan Yi, Korea Advanced Institute of Science and Technology
Hoon Choi, Korea Advanced Institute of Science and Technology
In-Cheol Park, Korea Advanced Institute of Science and Technology pp. 384
| Session 5B: Partitioning and Routing |
| Session 5C: Panel - Formal Verification: A New Standard CAD Tool for the Industrial Design Flow |
| Session 5D: Simulation for High-Level Design |
Simulation for High-Level Design
| Session 6A: Architectural Synthesis |
Min Xu, University of California, Irvine pp. 446
Jian Li, University of Illinois at Urbana-Champaign pp. 457
| Session 6B: Timing and Crosstalk in Interconnect |
Timing and Crosstalk in Interconnect
| Session 6C: Panel: Next Generation System Design Tools |
| Session 6D: IDDQ and Memory Testing |
| Session 7A: Microsystems |
R. Neul, Robert Bosch GmbH FhG-IIS/EAS pp. 510
V. Szekely, Technical University of Budapest, Dept. of Electron Devices
M. Rencz, Technical University of Budapest, Dept. of Electron Devices pp. 518
| Session 7B: Interconnect Modeling |
| Session 7C: Design for Manufacturability - Embedded Tutorial |
Design for Manufacturability - Embedded Tutorial
W. Maly, Carnegie Mellon University
P. Simon, Philips NV, Nijmegen, The Netherlands pp. 557
| Session 7D: Sequential Circuit Testing |
Sequential Circuit Testing
| Session 8A: Issues in Behavioral Synthesis |
Issues in Behavioral Synthesis
| Session 8B: Formal Equivalence Checking Using Decision Diagrams |
Formal Equivalence Checking Using Decision Diagrams
| Session 8C: Hot Topic: Silicon Debug of Systems-on-Chips |
| Session 8D: Characterization and Verification of Analogue Circuits |
Characterization and Verification of Analogue Circuits
M. Thole, Institut fuer Netzwerktheorie und Schaltungstechnik pp. 644
| Session 9A: Benchmark Circuits, Technology Mapping and Scan Chains |
Benchmark Circuits, Technology Mapping and Scan Chains
Nevin Kapur, CBL (Collaborative Benchmarking Laboratory) pp. 656
Aiguo Lu, Technical University of Munich pp. 664
| Session 9B: Physical to Gate Level Design for Low-Power |
Physical to Gate Level Design for Low-Power
| Session 9C: Hot Topic: Embedded Memory and Embedded Logic |
| Session 9D: Analogue Circuit Modeling and Design Methodology |
Analogue Circuit Modeling and Design Methodology
| Session 10A: Combinational Logical Synthesis |
Combinational Logical Synthesis
| Session 10B: High Level Power Estimation |
High Level Power Estimation
Massoud Pedram, University of Southern California, Los Angeles, CA 90089 pp. 774
| Session 10C: Petri Nets and Dedicated Formalisms |
Petri Nets and Dedicated Formalisms
Bill Lin, University of California, San Diego pp. 782
| Session 10D: Mixed-Signal Test and DFT |
Mixed-Signal Test and DFT
| Session 11A: Sequential Logic Synthesis |
Sequential Logic Synthesis
| Session 11B: High-Level Power Optimization |
High-Level Power Optimization
| Session 11C: System Architecture Design |
System Architecture Design
| Session 11D: Simulation and Test Tools for Analogue Circuits |
Simulation and Test Tools for Analogue Circuits
Mike Chou, Massachusetts Institute of Technology pp. 892
| Poster Session |
M.L. Flottes, Micro?lectronique de Montpellier,U.M. CNRS 9928
R. Pires, Micro?lectronique de Montpellier,U.M. CNRS 9928
B. Rouzeyre, Micro?lectronique de Montpellier,U.M. CNRS 9928
L. Volpe, Micro?lectronique de Montpellier,U.M. CNRS 9928 pp. 921
D. Heller, IRESTE, University of NANTES, FRANCE
F. Muller, IRESTE, University of NANTES, FRANCE pp. 927
A. Nunez, University of Las Palmas de Gran Canaria pp. 947
Jie Gong, Unified Design System Laboratory pp. 949
J. Uceda, Universidad Politecnica de Madrid pp. 955
H. Manhaeve, KHBO, Microelectronics Department, Oostende, Belgium pp. 959
M. Wolf, Otto-von-Guericke-University of Magdeburg
U. Kleine, Otto-von-Guericke-University of Magdeburg pp. 961
Anatoly Prihozhy, State University of Informatics and Radioelectronics of Belarus pp. 963
Th. Calin, Reliable Integrated Systems Group, TIMA/INPG pp. 987 Usage of this product signifies your acceptance of the Terms of Use.
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