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Design Automation and Test in Europe (DATE '98)
Hierarchical Characterization of Analog Integrated CMOS Circuits
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
Josef Eckmueller, Siemens AG, Munich
Martin Groepl, Siemens AG, Munich
Helmut E. Graeb, Techn. Univ. Munich
This paper presents a new method for hierarchical characterization of analog integrated circuits. For each circuit class, a fundamental set of performances is defined and extracted topology independently. A circuit being characterized is decomposed in general subcircuits. Sizing rules of these topology independent subcircuits are included into the characterization by functional constraints. In this way, bad circuit sizing is detected and located.
Index Terms:
hierarchical characterization - functional constraints - circuit performances - circuit class - topology independent - transistor pairs
Citation:
Josef Eckmueller, Martin Groepl, Helmut E. Graeb, "Hierarchical Characterization of Analog Integrated CMOS Circuits," date, pp.636, Design Automation and Test in Europe (DATE '98), 1998
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