Feb. 23, 1998 to Feb. 26, 1998
Ralf Reetz , Verysys GmbH
Klaus Schneider , Universit? at Karlsruhe
Thomas Kropf , Universit? at Karlsruhe
In this paper, we enrich VHDL with new specification constructs intended for hardware verification. Using our extensions, total correctness properties may now be stated whereas only partial correctness can be expressed using the standard VHDL assert statement. All relevant properties can now be specified in such a way that the designer does not need to use formalisms like temporal logics. As the specifications are independent from a certain formalism, there is no restriction to a certain hardware verification approach.
Ralf Reetz, Klaus Schneider, Thomas Kropf, "Formal Specification in VHDL for Hardware Verification", DATE, 1998, Design, Automation & Test in Europe Conference & Exhibition, Design, Automation & Test in Europe Conference & Exhibition 1998, pp. 257, doi:10.1109/DATE.1998.655865