This paper presents a proposal for enabling VHDL to better support reuse and collaboration. Base idea is passing on the adequate information to partners working in an object-oriented hardware design environment. Appropriate subgoals for achieving this are: ? an optimal mix of necessary abstraction and sufficient precision,? a formal description consisting of implementation constraints and knowledge requirements, and ? the non-formal concept of mutual consideration.Several loans are made from? the software domain: Java interfaces, type models, and the request for habitability,? the VHDL Annotation Language.This is not an experience report, for the idea of adopting the mentioned software concepts to hardware design is new. It is rather a guided tour to some "panorama views". Although they may not seem related to each other at first glance, they turn out to altogether support a common goal: understanding and communicating VHDL-based designs better.