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Paris, France
Feb. 23, 1998 to Feb. 26, 1998
ISBN: 0-8186-8359-7
pp: 66
Ishwar Parulkar , University of Southern California
Sandeep K. Gupta , University of Southern California
Melvin A. Breuer , University of Southern California
Built-in self-test (BIST) techniques modify functional hardware to give a data path the capability to test itself. The modification of data path registers into registers (BIST resources) that can generate pseudo-random test patterns and/or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis affect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a significant reduction in BIST area overhead and hence total area.
High-level synthesis, Built-in Self-test
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer, "Scheduling and Module Assignment for Reducing Bist Resources", DATE, 1998, Design, Automation & Test in Europe Conference & Exhibition, Design, Automation & Test in Europe Conference & Exhibition 1998, pp. 66, doi:10.1109/DATE.1998.655838
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