- D
- DAC
- 2003
- 40th Design Automation Conference (DAC'03)
| | This Publication | | | | | | | |
| | | | Bibliographic References | | | |
| | | | |
40th Design Automation Conference (DAC'03) Anaheim, CA June 02-June 06 ISBN: 1-58113-688-9 Table of Contents
 | SESSION 1: Special Session - Real Challenges and Solutions for Validating System-on-Chip |
 | SESSION 2: Panel - Reshaping EDA for Power |
 | SESSION 3: Design for Manufacturability and Global Routing |
P. Gupta, University of California at San Diego
J. Yang, University of Michigan at Ann Arbor pp. 16
Yu Chen, UCLA Computer Science Dept., Los Angeles, CA pp. 22
 | SESSION 4: Design Analysis Techniques |
 | SESSION 5: Embedded Hardware Design Case Studies |
N. Zervos, Ellemedia Technologies, Athens, Greece pp. 54
Yi Fan, UCLA Electrical Engineering Department pp. 60
 | SESSION 6: Special Session - Emerging Design and Tool Challenges in RF and Wireless Applications |
Seamless Multi-Radio Integration Challenges
John Wood, Agilent Technologies, Santa Rosa, CA pp. 85
 | SESSION 7: Panel - COT-Customer Owned Trouble |
 | SESSION 8: Power Grid Analysis and Optimization |
Bo Yao, University of California, San Diego pp. 105
Haihua Su, IBM Austin Research Lab, Austin, TX pp. 109
Kai Wang, University of California, Santa Barbara pp. 113
 | SESSION 9: Low-Power Embedded System Design |
Dexin Li, University of California, Irvine pp. 119
Taewhan Kim, Korea Advanced Institute of Science & Technology, Korea pp. 125
Gang Qu, University of Maryland, College Park pp. 131
 | SESSION 10: Cyclic and Non-Cyclic Combinational Circuit Synthesis |
 | SESSION 11: Managing Leakage Power |
 | SESSION 12: Panel - Emerging Markets: Design Goes Global |
 | SESSION 13: Timing-Oriented Placement |
Xin Yuan, University of California, Los Angeles pp. 208
 | SESSION 14: Model Order Reduction |
Emad Gad, Carleton University, Ontario, Canada pp. 238
 | SESSION 15: Issues in Partitioning & Design Space Exploration for Codesign |
Frank Vahid, UC Irvine; University of California, Riverside pp. 250
Kubilay Atasu, Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland
Laura Pozzi, Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland
Paolo Ienne, Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland pp. 256
Rainer Leupers, Aachen University of Technology (RWTH), Aachen, Germany
Heinrich Meyr, Aachen University of Technology (RWTH), Aachen, Germany pp. 262
 | SESSION 16: Special Session - Nano Technology: Design Implications and CAD Challenges |
 | SESSION 17: Panel - Mixed Signals on Mixed-Signal: the Right Next Technology |
 | SESSION 18: Simulation Coverage and Generation for Verification |
Shai Fine, IBM Research Laboratory in Haifa, Israel
Avi Ziv, IBM Research Laboratory in Haifa, Israel pp. 286
 | SESSION 19: Tool Support for Architectural Decisions in Embedded Systems |
Haris Lekatsas, NEC Labs America, Princeton, New Jersey; Vorras Corporation, Princeton, New Jersey
J? Henkel, NEC Labs America, Princeton, New Jersey pp. 306
 | SESSION 20: New Topics in Logic Synthesis |
 | SESSION 21: Special Session - Coping with Variability: The End of Deterministic Design |
Jim Tschanz, Circuit Research, Intel Labs, Hillsboro, OR
Vivek De, Circuit Research, Intel Labs, Hillsboro, OR pp. 338
 | SESSION 22: Panel - Fast, Cheap and Under Control: The Next Implementation Fabric |
 | SESSION 23: Testbench, Verification and Debugging: Practical Considerations |
Yuan Yu, Microsoft Research, Mountain View, CA pp. 356
Karen Yorav, Carnegie Mellon University, Pittsburgh, PA pp. 368
 | SESSION 24: Delay and Noise Modeling in the Nanometer Regime |
D. F. Wong, University of Illinois at Urbana-Champaign pp. 386
 | SESSION 25: Modeling Issues in the Design of Embedded Systems |
Alex Bobrek, Carnegie Mellon University, Pittsburgh, PA pp. 408
Pradeep Rao, Indian Institute of Science, Bangalore, India
S. K. Nandy, Indian Institute of Science, Bangalore, India pp. 412
 | SESSION 26: Special Session - How Application/Technology Evolutions Will Shape Classical EDA? |
Panel Discussion of Special Session 26: Platform Based Design vs. Network on Chip
 | SESSION 27: SAT and BDD Algorithms for Verification Tools |
Amit Goel, Carnegie Mellon University, Pittsburgh, PA pp. 431
Feng Lu, University of California at Santa Barbara
Li-C. Wang, University of California at Santa Barbara pp. 436
Kelvin Ng, University of British Columbia, Vancouver, BC
Jawahar Jain, Fujitsu Laboratories of America, Sunnyvale, CA pp. 442
 | SESSION 28: Elements of Functional and Performance Analysis |
Rolf Ernst, Technical University of Braunschweig, Germany pp. 454
Xi Chen, University of California at Riverside pp. 460
 | SESSION 29: Nonlinear Model Order Reduction |
Peng Li, Carnegie Mellon University, Pittsburgh, Pennsylvania pp. 472
Xin Li, Carnegie Mellon University, Pittsburgh, PA
Peng Li, Carnegie Mellon University, Pittsburgh, PA
Yang Xu, Carnegie Mellon University, Pittsburgh, PA pp. 478
Jacob White, Massachusetts Institute of Technology, Cambridge pp. 490
 | SESSION 30: Novel Techniques in High-Level Synthesis |
Manish Amde, Indian Institute of Technology, Bombay, India pp. 502
Byoungro So, University of Southern California / Information Sciences Institute, Marina del Rey, California
Pedro C. Diniz, University of Southern California / Information Sciences Institute, Marina del Rey, California
Mary W. Hall, University of Southern California / Information Sciences Institute, Marina del Rey, California pp. 514
 | SESSION 31: Mixed-Signal Design and Simulation |
Zhao Li, University of Washington, Seattle pp. 542
 | SESSION 32: Panel - Nanometer Design: Place Your Bets |
 | SESSION 33: Novel Self-Test Methods |
Li Chen, University of California at San Diego
Sujit Dey, University of California at San Diego pp. 548
Wei Li, Univ. of Iowa, Iowa City pp. 554
Marcelo Negreiros, Universidade Federal do Rio Grande do Sul - PPGC, Porto Alegre, RS, Brazil
Luigi Carro, Universidade Federal do Rio Grande do Sul - PPGC, Porto Alegre, RS, Brazil pp. 570
 | SESSION 34: Technology Mapping, Buffering, and Bus Design |
Bo Hu, Univ. of CA, Santa Barbara pp. 574
Zhuo Li, Texas A&M University, College Station, TX pp. 580
 | SESSION 35: Compilation Techniques for Reconfigurable Devices |
Heidi E. Ziegler, University of Southern California / Information Sciences Institute, Marina del Rey, CA
Mary W. Hall, University of Southern California / Information Sciences Institute, Marina del Rey, CA
Pedro C. Diniz, University of Southern California / Information Sciences Institute, Marina del Rey, CA pp. 610
 | SESSION 36: Architectural Power Estimation and Optimization |
 | SESSION 37: Panel - Libraries: Lifejacket or Straitjacket |
 | SESSION 38: Techniques for Reconfigurable Logic Applications |
 | SESSION 39: Test and Diagnosis for Complex Designs |
A. Krstic, University of California, Santa Barbara
L.-C. Wang, University of California, Santa Barbara
T. M. Mak, Intel Corporation, Santa Clara, CA pp. 668
Yu Huang, Mentor Graphics Co., Waltham, MA pp. 674
 | SESSION 40: Special Session - Highlights of ISSCC: High-Speed Heterogenous Design Techniques |
Jaeha Kim, True Circuits, Inc., Los Altos, CA
Jay Maxey, Texas Instruments Incorporated, Dallas, TX pp. 688
M. Borgatti, STMicroelectronics, Central R&D, Agrate Brianza, Italy
L. Cal?, STMicroelectronics, Central R&D, Agrate Brianza, Italy
G. De Sandre, STMicroelectronics, Central R&D, Agrate Brianza, Italy
B. For?, STMicroelectronics, Central R&D, Agrate Brianza, Italy
D. Iezzi, STMicroelectronics, Central R&D, Agrate Brianza, Italy
F. Lertora, STMicroelectronics, Central R&D, Agrate Brianza, Italy
G. Muzzi, STMicroelectronics, Central R&D, Agrate Brianza, Italy
M. Pasotti, STMicroelectronics, Central R&D, Agrate Brianza, Italy
M. Poles, STMicroelectronics, Central R&D, Agrate Brianza, Italy
P. L. Rolandi, STMicroelectronics, Central R&D, Agrate Brianza, Italy pp. 691
 | SESSION 41: Special Session - Highlights of ISSCC and The Design of State-of-the-Art Microprocessors |
Lisa Lacey, IBM TJ Watson Research Center, Yorktown Heights, NY
Greg Northrop, IBM TJ Watson Research Center, Yorktown Heights, NY pp. 696
 | SESSION 42: Panel - Formal Verification - Prove It or Pitch It |
 | SESSION 43: High Frequency Interconnect Modeling |
Zhenhai Zhu, Massachusetts Institute of Technology, Cambridge
Ben Song, Massachusetts Institute of Technology, Cambridge
Jacob White, Massachusetts Institute of Technology, Cambridge pp. 712
D. Goren, IBM Haifa Research and Development Labs, Israel
M. Zelikson, IBM Haifa Research and Development Labs, Israel
R. Gordin, IBM Haifa Research and Development Labs, Israel
I. A. Wagner, IBM Haifa Research and Development Labs, Israel
A. Barger, IBM Haifa Research and Development Labs, Israel
A. Amir, IBM Haifa Research and Development Labs, Israel
B. Livshitz, IBM Haifa Research and Development Labs, Israel
A. Sherman, IBM Haifa Research and Development Labs, Israel
R. Groves, IBM SiGe Model Development, East Fishkill
J. Park, IBM SiGe Model Development, East Fishkill
D. Jordan, IBM Design Automation Dept., Burlington
S. Strang, IBM Design Automation Dept., Burlington
R. Singh, IBM Design Automation Dept., Burlington
C. Dickey, IBM Design Automation Dept., Burlington
D. Harame, IBM Design Automation Dept., Burlington pp. 724
 | SESSION 44: Novel Approaches in Test Cost Reduction |
Shan Gu, Tsinghua University, Beijing, China
Yu-liang Wu, The Chinese Univ. of Hong Kong, Shatin N.T., Hong Kong pp. 744
 | SESSION 45: Retargetable Tools for Embedded Software |
 | SESSION 46: Special Session - ASIC Design in Nanometer Era - Dead or Alive? |
L. Pileggi, Carnegie Mellon University, Pittsburgh, Pennsylvania
H. Schmit, Carnegie Mellon University, Pittsburgh, Pennsylvania
V. Kheterpal, Carnegie Mellon University, Pittsburgh, Pennsylvania
A. Koorapaty, Carnegie Mellon University, Pittsburgh, Pennsylvania
C. Patel, Carnegie Mellon University, Pittsburgh, Pennsylvania
V. Rovner, Carnegie Mellon University, Pittsburgh, Pennsylvania
K. Y. Tong, Carnegie Mellon University, Pittsburgh, Pennsylvania pp. 782
John Cohn, IBM Microelectronics, Essex Jn, VT pp. 788
 | SESSION 47: Floorplanning and Placement |
Bo Yao, University of California, San Diego pp. 794
Bo Hu, Univ. of California, Santa Barbara pp. 800
Yuchun Ma, Tsinghua University, Beijing, China
Song Chen, Tsinghua University, Beijing, China
Yici Cai, Tsinghua University, Beijing, China
Jun Gu, Science & Technology University of Hong Kong pp. 806
Jer-Ming Hsu, National Center for High-Performance Computing, Hsinchu, Taiwan pp. 812
 | SESSION 48: Advances in SAT |
 | SESSION 49: Novel Design Methodologies and Signal Integrity |
Kaijian Shi, Professional Services, Synopsys Inc., Dallas, TX pp. 850
Yajun Ran, University of California, Santa Barbara pp. 860
 | SESSION 50: Memory Optimization for Embedded Systems |
Prabhat Jain, Massachusetts Institute of Technology, Cambridge pp. 869
Yoonseo Choi, Korea Advanced Institute of Science and Technology, KOREA
Taewhan Kim, Korea Advanced Institute of Science and Technology, KOREA pp. 881
W. Zhang, The Pennsylvania State University, University Park
G. Chen, The Pennsylvania State University, University Park
M. Kandemir, The Pennsylvania State University, University Park pp. 887
 | SESSION 51: Special Session - Design Automation for Quantum Circuits |
 | SESSION 52: Energy-Aware System Design |
 | SESSION 53: Budgeting, Simulation and Statistical Timing |
S. Ghiasi, University of California, Los Angeles (UCLA) pp. 920
J. A. G. Jess, Eindhoven University of Technology, The Netherlands
K. Kalafala, IBM Microelectronics Division, East Fishkill, NY
S. R. Naidu, Eindhoven University of Technology, The Netherlands
C. Visweswariah, IBM Thomas J. Watson Research Center, Yorktown Heights, NY pp. 932
 | SESSION 54: Interconnect Noise Avoidance Methodologies & Slew Rate Prediction |
Yajun Ran, University of California, Santa Barbara pp. 944
 | SESSION 55: Analog Design Space Exploration | Usage of this product signifies your acceptance of the Terms of Use.
| | | | | | | |