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39th Design Automation Conference (DAC'02)
New Orleans, LA
June 10-June 14
ISBN: 1-58113-461-4
Table of Contents
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Session 1 - PANEL: Wall Street Evaluates EDA
Session 2 - Web and IP Based Design
Michael J. Wirthlin, Brigham Young University, Provo, UT
Brian McMurtrey, Brigham Young University, Provo, UT
pp. 2
Seapahn Megerian, University of California Los Angeles
Milenko Drinic, University of California Los Angeles
Miodrag Potkonjak, University of California Los Angeles
pp. 8
Milenko Drinic, University of California, Los Angeles
Darko Kirovski, Microsoft Research, Redmond, WA
pp. 18
Session 3 - Design Innovations for Embedded Processors
Achim Nohl, Integrated Signal Processing Systems, Aachen, Germany
Gunnar Braun, Integrated Signal Processing Systems, Aachen, Germany
Oliver Schliebusch, Integrated Signal Processing Systems, Aachen, Germany
Rainer Leupers, Integrated Signal Processing Systems, Aachen, Germany
Heinrich Meyr, Integrated Signal Processing Systems, Aachen, Germany
Andreas Hoffmann, LISATek Inc., Menlo Park, CA
pp. 22
Roman Lysecky, University of California, Riverside
Susan Cotterell, University of California, Riverside
Frank Vahid, University of California, Riverside
pp. 28
Session 4 - Passive Model Order Reduction
Q. Su, Purdue University, West Lafayette, IN
V. Balakrishnan, Purdue University, West Lafayette, IN
C.-K. Koh, Purdue University, West Lafayette, IN
pp. 40
Joel Phillips, Cadence Design Systems, San Jose, CA
Luca Daniel, University of California Berkeley
L. Miguel Silveira, INESC ID - Cadence Euro Labs
pp. 52
Session 5 - New Perspectives in Physical Design
Xiaoliang Bai, UC San Diego, La Jolla
Chandu Visweswariah, IBM T. J. Watson Research Center, Yorktown Heights, NY
Philip N. Strenski, IBM T. J. Watson Research Center, Yorktown Heights, NY
David J. Hathaway, IBM Microelectronics, Essex Junction, VT
pp. 58
Haihu Su, IBM Corp., Austin, TX
Jiang Hu, IBM Corp., Austin, TX
Sachin S. Sapantnekar, Univ. of Minnesota, Minneapolis
Sani R. Nassif, IBM Corp., Austin, TX
pp. 64
Parivallal Kannan, University of Texas at Dallas
Shankar Balachandran, University of Texas at Dallas
Dinesh Bhatia, University of Texas at Dallas
pp. 70
Session 6 - PANEL: Tools or Users: Which is the Bigger Bottleneck?
Session 7 - Special Session: Life after CMOS: Imminent or Irrelevant?
George Sery, Intel Corporation, Santa Clara, CA
Shekhar Borkar, Intel Corporation, Santa Clara, CA
Vivek De, Intel Corporation, Santa Clara, CA
pp. 78
Adrian M. Ionescu, Swiss Federal Institute of Technology Lausanne, Switzerland
Michel J. Declercq, Swiss Federal Institute of Technology Lausanne, Switzerland
Santanu Mahapatra, Swiss Federal Institute of Technology Lausanne, Switzerland
Kaustav Banerjee, Stanford University, CA
Jacques Gautier, CEA-DRT - LETI/DTS - CEA/GRE
pp. 88
R. Martel, IBM T. J. Watson Research Center, Yorktown Heights, NY
V. Derycke, IBM T. J. Watson Research Center, Yorktown Heights, NY
J. Appenzeller, IBM T. J. Watson Research Center, Yorktown Heights, NY
S. Wind, IBM T. J. Watson Research Center, Yorktown Heights, NY
Ph. Avouris, IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 94
Session 8 - Formal Verification
Alfred K?lbl, Technical University of Munich, Germany
James Kukula, Synopsys Inc., Beaverton, OR
Kurt Antreich, Technical University of Munich, Germany
Robert Damiano, Synopsys Inc., Beaverton, OR
pp. 105
Scott Hazelhurst, University of the Witwatersrand, Johannesburg, South Africa
Osnat Weissberg, Intel Corporation, Haifa, Israel
Gila Kamhi, Intel Corporation, Haifa, Israel
Limor Fix, Intel Corporation, Haifa, Israel
pp. 111
Gianpiero Cabodi, Politecnico di Torino, Turin, Italy
Paolo Camurati, Politecnico di Torino, Turin, Italy
Stefano Quer, Politecnico di Torino, Turin, Italy
pp. 117
Session 9 - High Level Specification and Design
Arindam Chakrabarti, UC Berkeley
Pallab Dasgupta, Indian Institute of Technology Kharagpur, India
P. P. Chakrabarti, Indian Institute of Technology Kharagpur, India
Ansuman Banerjee, Indian Institute of Technology Kharagpur, India
pp. 141
Session 10 - Timing Abstraction
Ajay J. Daga, Synopsys, Inc., Hillsboro, OR
Loa Mize, Synopsys, Inc., Hillsboro, OR
Subramanyam Sripada, Synopsys, Inc., Hillsboro, OR
Chris Wolff, Synopsys, Inc., Hillsboro, OR
Qiuyang Wu, Synopsys, Inc., Hillsboro, OR
pp. 146
Cho W. Moon, Cadence Design Systems, San Diego, CA
Harish Kriplani, Cadence Design Systems, San Diego, CA
Krishna P. Belkhale, Cadence Design Systems, San Diego, CA
pp. 152
Martin Foltin, Hewlett Packard Corporation, Fort Collins, CO
Brian Foutz, IBM Test Design Automation, Endicott, NY
Sean Tyler, Hewlett Packard Corporation, Fort Collins, CO
pp. 158
Session 11 - Special Session: E-Textiles
Sungmee Park, Georgia Institute of Technology, Atlanta
Kenneth Mackenzie, Georgia Institute of Technology, Atlanta
Sundaresan Jayaraman, Georgia Institute of Technology, Atlanta
pp. 170
Session 12 - PANEL: Analog Intellectual Property: Now? Or Never?
Session 13 - Low-Power System Design
Yumin Zhang, Synopsys, Inc., Mountain View, CA
Xiaobo (Sharon) Hu, University of Notre Dame, IN
Danny Z. Chen, University of Notre Dame, IN
pp. 183
Daler Rakhmatov, University of Arizona, Tucson
Sarma Vrudhula, University of Arizona, Tucson
Chaitali Chakrabarti, Arizona State University, Tempe
pp. 189
I. Kadayif, Pennsylvania State University, University Park
M. Kandemir, Pennsylvania State University, University Park
M. Karakoy, Imperial College, London, UK
pp. 195
Session 14 - Fabric-Driven Logic Synthesis
Fan Mo, University of California, Berkeley
Robert K. Brayton, University of California, Berkeley
pp. 201
Junhyung Um, Korea Advanced Institute of Science and Technology
Taewhan Kim, Korea Advanced Institute of Science and Technology
pp. 207
Session 15 - Memory Management and Address Optimization in Embedded Systems
V. De La Luz, Pennsylvania State University, University Park
M. Kandemir, Pennsylvania State University, University Park
I. Kolcu, UMIST, Manchester, UK
pp. 213
Mahmut Kandemir, Pennsylvania State University, University Park
J. Ramanujam, Louisiana State University, Baton Rouge
A. Choudhary, Northwestern University, Evanston, IL
pp. 219
Yoonseo Choi, Korea Advanced Institute of Science and Technology, KOREA
Taewhan Kim, Korea Advanced Institute of Science and Technology, KOREA
pp. 225
Session 16 - Special Session: Optics: Lighting the Way to EDA Riches?
James G. Maloney, PhotonEx, Maynard, MA
Brian E. Brewington, PhotonEx, Maynard, MA
Curtis R. Menyuk, PhotonEx, Maynard, MA
pp. 235
Timothy P. Kurzweg, University of Pittsburgh, PA
Steven P. Levitan, University of Pittsburgh, PA
Jose A. Martinez, University of Pittsburgh, PA
Mark Kahrs, University of Pittsburgh, PA
Donald M. Chiarulli, University of Pittsburgh, PA
pp. 236
Session 17 - PANEL: Nanometer Design: What Hurts Next...?
Session 18 - Novel DFT, BIST and Diagnosis Techniques
Miron Abramovici, Agere Systems - Murray Hill, NJ
Xiaoming Yu, University of Illinois - Urbana, IL
Elizabeth M. Rudnick, University of Illinois - Urbana, IL
pp. 243
Peter Wohl, Synopsys Inc., Williston, VT
John A. Waicukauski, Synopsys Inc., Tualatin, OR
Sanjay Patel, Synopsys Inc., Beaverton, OR
Greg Maston, Synopsys Inc., Denver, CO
pp. 249
Irith Pomeranz, Purdue University, W. Lafayette, IN
Sandip Kundu, Intel Corp., Austin, TX
Sudhakar M. Reddy, University of Iowa, Iowa City
pp. 255
Li Chen, University of California at San Diego, La Jolla
Sujit Dey, University of California at San Diego, La Jolla
pp. 259
Session 19 - Case Studies in Embedded System Design
Xun Liu, University of Michigan, Ann Arbor
Marios C. Papaefthymiou, University of Michigan, Ann Arbor
pp. 263
Daniel Ragan, University of Maryland, College Park
Peter Sandborn, University of Maryland, College Park
Paul Stoaks, Foresight-Systems, Inc., Austin, Texas
pp. 269
Session 20 - Theoretical Foundations of Embedded System Design
Ingo Sander, Royal Institute of Technology, Stockholm, Sweden
Axel Jantsch, Royal Institute of Technology, Stockholm, Sweden
pp. 281
Kai Richter, Technical University of Braunschweig, Germany
Dirk Ziegenbein, Technical University of Braunschweig, Germany
Marek Jersak, Technical University of Braunschweig, Germany
Rolf Ernst, Technical University of Braunschweig, Germany
pp. 287
Session 21 - Equivalence Verification
Simon Jolly, FourSticks Pty. Ltd., Frewville, South Australia
Atanas Parashkevov, Motorola Inc., South Australia
Tim McDougall, Motorola Inc., South Australia
pp. 299
Session 22 - PANEL: Whither (or Wither?) ASIC Handoff
Session 23 - Embedded Software Automation: From Specification to Binary
Armita Peymandoust, Stanford University, CA
Tajana Simunic, HP Labs & Stanford University, Palo Alto, CA
Giovanni De Micheli, Stanford University, CA
pp. 325
Maghsoud Abbaspour, University of Toronto, Canada
Jianwen Zhu, University of Toronto, Canada
pp. 331
Session 24 - Applications of Reconfigurable Computing
Edson L. Horta, Universidade de San P?ulo, Brazil
John W. Lockwood, Washington University, Saint Louis, MO
David E. Taylor, Washington University, Saint Louis, MO
David Parlour, Xilinx, Inc, San Jose, CA
pp. 343
Jinghuan Chen, University of Minnesota, Minneapolis
Jaekyun Moon, University of Minnesota, Minneapolis
Kia Bazargan, University of Minnesota, Minneapolis
pp. 349
Session 25 - New Test Methods Targeting Non-Classical Faults
A. Krstic, University of California, Santa Barbara
W.-C. Lai, University of California, Santa Barbara
L. Chen, University of California, San Diego
K.-T. Cheng, University of California, Santa Barbara
S. Dey, University of California, San Diego
pp. 355
Swarup Bhunia, Purdue University, Indiana, USA
Kaushik Roy, Purdue University, Indiana, USA
Jaume Segura, Balearic Islands University, Spain
pp. 361
Amir Attarha, The University of Texas at Dallas
Mehrdad Nourani, The University of Texas at Dallas
pp. 367
Jing-Jia Liou, UC-Santa Barbara
Li-C. Wang, UC-Santa Barbara
Kwang-Ting Cheng, UC-Santa Barbara
Jennifer Dworak, Texas A&M University
M. Ray Mercer, Texas A&M University
Rohit Kapur, Synopsys Inc.
Thomas W. Williams, Synopsys Inc.
pp. 371
Session 26 - Special Session: How Do You Design a 10M Gate ASIC?
Session 27 - Power Distribution Issues
Yahong Cao, University of Wisconsin at Madison
Yu-Min Lee, University of Wisconsin at Madison
Tsung-Hao Chen, University of Wisconsin at Madison
Charlie Chung-Ping Chen, University of Wisconsin at Madison
pp. 379
Srinivas Bodapati, University of Illinois at Urbana-Champaign
Farid N. Najm, University of Toronto, Canada
pp. 385
Brian W. Amick, Sun Microsystems Inc., Austin, TX
Claude R. Gauthier, Sun Microsystems Inc., Sunnyvale, CA
Dean Liu, Sun Microsystems Inc., Sunnyvale, CA
pp. 391
Mustafa Badaroglu, IMEC, Leuven, Belgium; ESAT - KU Leuven, Belgium
Kris Tiri, IMEC, Leuven, Belgium; UCLA
St?phane Donnay, IMEC, Leuven, Belgium
Piet Wambacq, IMEC, Leuven, Belgium
Georges Gielen, ESAT - KU Leuven, Belgium
Hugo De Man, IMEC, Leuven, Belgium; ESAT - KU Leuven, Belgium
pp. 399
Session 28 - Advances in Synthesis
Alex Kondratyev, Cadence Berkeley Laboratory, Berkeley, CA
Kelvin Lwin, Reshape Inc., Mountain View, CA
pp. 411
Christos P. Sotiriou, Institute of Computer Science (ICS), Foundation of Research and Technology - Hellas (FORTH), Greece
pp. 415
Kazuo Iwama, Kyoto Univ., Japan
Yahiko Kambayashi, Kyoto Univ., Japan
Shigeru Yamashita, NTT Communication Science Labs., Japan
pp. 419
Anna Bernasconi, University of Pisa, Italy
Valentina Ciriani, University of Pisa, Italy
Fabrizio Luccio, University of Pisa, Italy
Linda Pagli, University of Pisa, Italy
pp. 425
Session 29 - Analog Synthesis & Design Methodology
Hongzhou Liu, Carnegie Mellon University, Pittsburgh, Pennsylvania
Amit Singhee, Carnegie Mellon University, Pittsburgh, Pennsylvania
Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, Pennsylvania
L. Richard Carley, Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 437
Ovidiu Bajdechi, Delft University of Technology, The Netherlands
Georges Gielen, Katholieke Universiteit Leuven, Leuven, Belgium
Johan H. Huijsing, Delft University of Technology, The Netherlands
pp. 443
J. Vandenbussche, Katholieke Universiteit Leuven, Heverlee, Belgium
K. Uyttenhove, Katholieke Universiteit Leuven, Heverlee, Belgium
E. Lauwers, Katholieke Universiteit Leuven, Heverlee, Belgium
M. Steyaert, Katholieke Universiteit Leuven, Heverlee, Belgium
G. Gielen, Katholieke Universiteit Leuven, Heverlee, Belgium
pp. 449
Session 30 - Low-Power Physical Design
Ashok K. Murugavel, University of South Florida, Tampa, Florida
N. Ranganathan, University of South Florida, Tampa, Florida
pp. 455
Seong-Ook Jung, University of Illinois, Urbana
Ki-Wook Kim, Pluris Incorporation, Cupertino, CA
Sung-Mo Kang, University of California, Santa Cruz
pp. 467
Amit Agarwal, Purdue University, West Lafayette, IN
Hai Li, Purdue University, West Lafayette, IN
Kaushik Roy, Purdue University, West Lafayette, IN
pp. 473
Session 31 - PANEL: Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible or Mission Irrelevant?
Session 32 - Multi-Voltage, Multi-Threshold Design
Mohab Anis, University of Waterloo, Canada
Shawki Areibi, University of Guelph, Canada
Mohamed Mahmoud, University of Waterloo, Canada
Mohamed Elmasry, University of Waterloo, Canada
pp. 480
Tanay Karnik, Circuit Research, Intel Labs, Hillsboro, OR
Yibin Ye, Circuit Research, Intel Labs, Hillsboro, OR
James Tschanz, Circuit Research, Intel Labs, Hillsboro, OR
Liqiong Wei, Circuit Research, Intel Labs, Hillsboro, OR
Steven Burns, Strategic CAD, Intel Labs, Hillsboro, OR
Venkatesh Govindarajulu, Circuit Research, Intel Labs, Hillsboro, OR
Vivek De, Circuit Research, Intel Labs, Hillsboro, OR
Shekhar Borkar, Circuit Research, Intel Labs, Hillsboro, OR
pp. 486
Dong-In Kang, University of Southern California/Information Sciences Institute, Arlington, VA
Jinwoo Suh, University of Southern California/Information Sciences Institute, Arlington, VA
Stephen P. Crago, University of Southern California/Information Sciences Institute, Arlington, VA
pp. 492
Session 33 - Advanced Simulation Techniques
Session 34 - Design Methodologies Meet Network Applications
Ch. Ykman-Couvreur, IMEC, Leuven, Belgium
J. Lambrecht, IMEC, Leuven, Belgium
D. Verkest, IMEC, Leuven, Belgium
F. Catthoor, Katholieke Univ. Leuven; IMEC, Leuven, Belgium
A. Nikologiannis, ELLEMEDIA technologies, Athens, Greece
G. Konstantoulakis, Inaccess Networks SA, Athens, Greece
pp. 518
David Whelihan, Carnegie Mellon University, Pittsburgh, PA
Herman Schmit, Carnegie Mellon University, Pittsburgh, PA
pp. 530
Session 35 - Advances in Analog Modeling
Piet Vanassche, Katholieke Universiteit Leuven, Belgium
Georges Gielen, Katholieke Universiteit Leuven, Belgium
Willy Sansen, Katholieke Universiteit Leuven, Belgium
pp. 536
Walter Hartong, University of Hannover, Germany
Lars Hedrich, University of Hannover, Germany
Erich Barke, University of Hannover, Germany
pp. 542
Jochen Mades, Infineon Technologies AG, Munich, Germany
Manfred Glesner, Darmstadt University of Technology, Germany
pp. 548
Session 36 - Advances in Timing and Simulation
Jing-Jia Liou, University of California, Santa Barbara
Angela Krstic, University of California, Santa Barbara
Li-C. Wang, University of California, Santa Barbara
Kwang-Ting Cheng, University of California, Santa Barbara
pp. 566
Session 37 - PANEL: Formal Verification Methods: Getting around the Brick Wall
Session 38 - Routing and Buffering
Milos Hrkic, University of Illinois at Chicago
John Lillis, University of Illinois at Chicago
pp. 578
Hua Xiang, University of Texas at Austin
Xiaoping Tang, University of Texas at Austin; Silicon Perspective, A Cadence Company, Santa Clara, CA
D. F. Wong, University of Texas at Austin
pp. 584
Narendra V. Shenoy, Synopsys Inc., Mountain View, CA
William Nicholls, Synopsys Inc., Hillsboro, OR
pp. 590
Session 39 - System on Chip Design
Ferid Gharsalli, TIMA laboratory, France
Samy Meftali, TIMA laboratory, France
Fr?d?ric Rousseau, TIMA laboratory, France
Ahmed A. Jerraya, TIMA laboratory, France
pp. 596
M. C. Molina, Universidad Complutense de Madrid, Spain
J. M. Mend?as, Universidad Complutense de Madrid, Spain
R. Hermida, Universidad Complutense de Madrid, Spain
pp. 612
Session 40 - Timing Analysis and Memory Optimization for Embedded Systems
Samarjit Chakraborty, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Thomas Erlebach, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Simon K?, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Lothar Thiele, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
pp. 616
Fabian Wolf, Volkswagen AG, Wolfsburg, Germany
Jan Staschulat, Technical University of Braunschweig, Germany
Rolf Ernst, Technical University of Braunschweig, Germany
pp. 622
M. Kandemir, Pennsylvania State University, University Park
A. Choudhary, Northwestern University, Evanston, IL
pp. 628
Session 41 - Processors and Acclerators for Embedded Applications
Nick Richardson, STMicroelectronics, Inc., San Diego, CA
Lun Bin Huang, STMicroelectronics, Inc., San Diego, CA
Razak Hossain, STMicroelectronics, Inc., San Diego, CA
Tommy Zounes, STMicroelectronics, Inc., San Diego, CA
Naresh Soni, STMicroelectronics, Inc., San Diego, CA
Julian Lewis, STMicroelectronics, Inc., UK
pp. 640
Gokhan Memik, University of California, Los Angeles
William H. Mangione-Smith, University of California, Los Angeles
pp. 646
Session 42 - PANEL: What's the Next EDA Driver?
Session 43 - Cross-Talk Noise Analysis and Management
Sarma B. K. Vrudhula, Univ. of Arizona, Tucson
David Blaauw, Univ. of Michigan, Ann Arbor
Supamas Sirichotiyakul, Sun Microsystems, Boston, MA
pp. 653
Paul B. Morton, University of California at Santa Cruz
Wayne Dai, University of California at Santa Cruz
pp. 659
James D. Z. Ma, University of Wisconsin, Madison
Lei He, University of Wisconsin, Madison
pp. 669
Session 44 - Test Cost Reduction for SOCS
Douglas Kay, Cisco Systems, San Jose, CA
Sung Chung, Cisco Systems, San Jose, CA
Samiha Mourad, Santa Clara University, CA
pp. 679
Session 45 - Scheduling Techniques for Embedded Systems
V. Delaluz, The Pennsylvania State University, University Park
A. Sivasubramaniam, The Pennsylvania State University, University Park
M. Kandemir, The Pennsylvania State University, University Park
N. Vijaykrishnan, The Pennsylvania State University, University Park
M. J. Irwin, The Pennsylvania State University, University Park
pp. 697
I. Kadayif, Pennsylvania State University, University Park
M. Kandemir, Pennsylvania State University, University Park
U. Sezer, University of Wisconsin, Madison
pp. 703
Session 46 - Special Session: Designing SoCs for Yield Improvement
Miron Abramovici, Agere Systems, Murray Hill, NJ
Charles Stroud, University of North Carolina, Charlotte
Marty Emmert, Wright State University, Dayton, OH
pp. 713
Session 47 - Advances in SAT
Fadi A. Aloul, University of Michigan, Ann Arbor
Arathi Ramani, University of Michigan, Ann Arbor
Igor L. Markov, University of Michigan, Ann Arbor
Karem A. Sakallah, University of Michigan, Ann Arbor
pp. 731
Fadi A. Aloul, University of Michigan
Brian D. Sierawski, University of Michigan
Karem A. Sakallah, University of Michigan
pp. 737
Slawomir Pilarski, Synopsys, Inc., Hillsboro, OR
Gracia Hu, Synopsys, Inc., Hillsboro, OR
pp. 743
Malay K Ganai, NEC USA CCRL, Princeton NJ
Lintao Zhang, Princeton University
Pranav Ashar, NEC USA CCRL, Princeton NJ
Aarti Gupta, NEC USA CCRL, Princeton NJ
Sharad Malik, Princeton University
pp. 747
Session 48 - Inductance and Substrate Analysis
Hemant Mahawar, Texas A&M University, College Station
Vivek Sarin, Texas A&M University, College Station
Weiping Shi, Texas A&M University, College Station
pp. 751
Tao Lin, Carnegie Mellon University, Pittsburgh, PA
Michael W. Beattie, Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA
pp. 757
Raguraman Venkatesan, Georgia Institute of Technology, Atlanta
Jeffrey A. Davis, Georgia Institute of Technology, Atlanta
James D. Meindl, Georgia Institute of Technology, Atlanta
pp. 763
Adil Koukab, Swiss Federal Institute of Technology (EPFL), Switzerland
Catherine Dehollain, Swiss Federal Institute of Technology (EPFL), Switzerland
Michel Declercq, Swiss Federal Institute of Technology (EPFL), Switzerland
pp. 767
E. Schrik, Delft University of Technology, The Netherlands
N.P. van der Meijs, Delft University of Technology, The Netherlands
pp. 771
Session 49 - Development of Processors and Communication Networks for Embedded Systems
Alessandro Pinto, UC Berkeley EECS Department
Luca P. Carloni, UC Berkeley EECS Department
Alberto L. Sangiovanni-Vincentelli, UC Berkeley EECS Department
pp. 783
W. Ces?rio, TIMA Laboratory, SLS Group, France
A. Baghdadi, TIMA Laboratory, SLS Group, France
L. Gauthier, TIMA Laboratory, SLS Group, France
D. Lyonnard, TIMA Laboratory, SLS Group, France
G. Nicolescu, TIMA Laboratory, SLS Group, France
Y. Paviot, TIMA Laboratory, SLS Group, France
S. Yoo, TIMA Laboratory, SLS Group, France
A. A. Jerraya, TIMA Laboratory, SLS Group, France
M. Diaz-Nava, STMicroelectronics, France
pp. 789
Girish Varatkar, Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu, Carnegie Mellon University, Pittsburgh, PA
pp. 795
Session 50 - Moving Towards More Effective Validation
Oded Lachish, IBM Research Laboratory in Haifa, Haifa University, Israel
Eitan Marcus, IBM Research Laboratory in Haifa, Haifa University, Israel
Shmuel Ur, IBM Research Laboratory in Haifa, Haifa University, Israel
Avi Ziv, IBM Research Laboratory in Haifa, Haifa University, Israel
pp. 807
Shuo Sheng, Rutgers University, Piscataway, NJ
Koichiro Takayama, Fujitsu Labs. of America Inc., Sunnyvale, CA
Michael S. Hsiao, Virginia Tech, Blacksburg, VA
pp. 813
Session 51 - Special Session: Energy Efficient Mobile Computing
Carla F. Chiasserini, Dip. di Elettronica Politecnico di Torino, Italy
Pavan Nuggehalli, Dept. of ECE, UCSD
Vikram Srinivasan, Dept. of ECE, UCSD
pp. 824
Michiel Steyaert, Katholieke Universiteit Leuven, Belgium
Peter Vancorenland, Katholieke Universiteit Leuven, Belgium
pp. 836
Session 52 - Floorplanning and Placement
Jai-Ming Lin, National Chiao Tung University, Taiwan
Yao-Wen Chang, National Taiwan University, Taiwan
pp. 842
Xiaoping Tang, University of Texas at Austin; Silicon Perspective, A Cadence Company, Santa Clara, CA
D. F. Wong, University of Texas at Austin
pp. 848
Session 53 - Circuit Effects in Static Timing
Lauren Hui Chen, Avant! Corp., Fremont, CA
Malgorzata Marek-Sadowska, University of California, Santa Barbara
Forrest Brewer, University of California, Santa Barbara
pp. 860
Seung Hoon Choi, Purdue University, West Lafayette, IN
Florentin Dartu, Intel Corporation, Hillsboro, OR
Kaushik Roy, Purdue University, West Lafayette, IN
pp. 870
Jaesik Lee, Univ of Illinois, Urbana
Ki-Wook Kim, Pluris Incorporation, Cupertino, CA
Sung-Mo Kang, University of California, Santa Cruz
pp. 874
Session 54 - Design Space Exploration for Embedded Systems
Lothar Thiele, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Samarjit Chakraborty, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Matthias Gries, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Simon K?, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
pp. 880
A. Bona, ALaRI, Lugano, Switzerland
M. Sami, Politecnico di Milano, Italy
D. Sciuto, Politecnico di Milano, Italy
C. Silvano, Universit? degli Studi di Milano, Italy
V. Zaccaria, Politecnico di Milano, Italy
R. Zafalon, STMicroelectronics, Agrate B. (MI), Italy
pp. 886
Yongsoo Joo, Seoul National University, Korea
Yongseok Choi, Seoul National University, Korea
Hojun Shim, Seoul National University, Korea
Hyung Gyu Lee, Seoul National University, Korea
Kwanho Kim, Seoul National University, Korea
Naehyuck Chang, Seoul National University, Korea
pp. 892
Session 55 - Behavioral Synthesis
Timothy Kam, Intel Incorporated, Hillsboro, Oregon
Michael Kishinevsky, Intel Incorporated, Hillsboro, Oregon
Shai Rotem, Intel Incorporated, Hillsboro, Oregon
Nick Savoiu, University of California, Irvine
Nikil Dutt, University of California, Irvine
Rajesh Gupta, University of California, Irvine
Alex Nicolau, University of California, Irvine
pp. 898
Jennifer L. Wong, Univ. of California, Los Angeles
Seapahn Megerian, Univ. of California, Los Angeles
Miodrag Potkonjak, Univ. of California, Los Angeles
pp. 904
Farinaz Koushanfar, University of California, Berkeley
Jennifer L. Wong, University of California, Los Angeles
Jessica Feng, University of California, Los Angeles
Miodrag Potkonjak, University of California, Los Angeles
pp. 910
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