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- DAC
- 2002
- 39th Design Automation Conference (DAC'02)
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39th Design Automation Conference (DAC'02) New Orleans, LA June 10-June 14 ISBN: 1-58113-461-4 Table of Contents
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 | Session 1 - PANEL: Wall Street Evaluates EDA |
 | Session 2 - Web and IP Based Design |
 | Session 3 - Design Innovations for Embedded Processors |
Achim Nohl, Integrated Signal Processing Systems, Aachen, Germany
Gunnar Braun, Integrated Signal Processing Systems, Aachen, Germany
Heinrich Meyr, Integrated Signal Processing Systems, Aachen, Germany pp. 22
 | Session 4 - Passive Model Order Reduction |
Q. Su, Purdue University, West Lafayette, IN
C.-K. Koh, Purdue University, West Lafayette, IN pp. 40
 | Session 5 - New Perspectives in Physical Design |
 | Session 6 - PANEL: Tools or Users: Which is the Bigger Bottleneck? |
 | Session 7 - Special Session: Life after CMOS: Imminent or Irrelevant? |
Vivek De, Intel Corporation, Santa Clara, CA pp. 78
R. Martel, IBM T. J. Watson Research Center, Yorktown Heights, NY
V. Derycke, IBM T. J. Watson Research Center, Yorktown Heights, NY
J. Appenzeller, IBM T. J. Watson Research Center, Yorktown Heights, NY
S. Wind, IBM T. J. Watson Research Center, Yorktown Heights, NY
Ph. Avouris, IBM T. J. Watson Research Center, Yorktown Heights, NY pp. 94
 | Session 8 - Formal Verification |
 | Session 9 - High Level Specification and Design |
 | Session 10 - Timing Abstraction |
Sean Tyler, Hewlett Packard Corporation, Fort Collins, CO pp. 158
 | Session 11 - Special Session: E-Textiles |
 | Session 12 - PANEL: Analog Intellectual Property: Now? Or Never? |
 | Session 13 - Low-Power System Design |
I. Kadayif, Pennsylvania State University, University Park
M. Kandemir, Pennsylvania State University, University Park pp. 195
 | Session 14 - Fabric-Driven Logic Synthesis |
Fan Mo, University of California, Berkeley pp. 201
Junhyung Um, Korea Advanced Institute of Science and Technology
Taewhan Kim, Korea Advanced Institute of Science and Technology pp. 207
 | Session 15 - Memory Management and Address Optimization in Embedded Systems |
V. De La Luz, Pennsylvania State University, University Park
M. Kandemir, Pennsylvania State University, University Park pp. 213
Yoonseo Choi, Korea Advanced Institute of Science and Technology, KOREA
Taewhan Kim, Korea Advanced Institute of Science and Technology, KOREA pp. 225
 | Session 16 - Special Session: Optics: Lighting the Way to EDA Riches? |
 | Session 17 - PANEL: Nanometer Design: What Hurts Next...? |
 | Session 18 - Novel DFT, BIST and Diagnosis Techniques |
Li Chen, University of California at San Diego, La Jolla
Sujit Dey, University of California at San Diego, La Jolla pp. 259
 | Session 19 - Case Studies in Embedded System Design |
Xun Liu, University of Michigan, Ann Arbor pp. 263
 | Session 20 - Theoretical Foundations of Embedded System Design |
Ingo Sander, Royal Institute of Technology, Stockholm, Sweden
Axel Jantsch, Royal Institute of Technology, Stockholm, Sweden pp. 281
Kai Richter, Technical University of Braunschweig, Germany
Rolf Ernst, Technical University of Braunschweig, Germany pp. 287
 | Session 21 - Equivalence Verification |
Simon Jolly, FourSticks Pty. Ltd., Frewville, South Australia pp. 299
 | Session 22 - PANEL: Whither (or Wither?) ASIC Handoff |
 | Session 23 - Embedded Software Automation: From Specification to Binary |
 | Session 24 - Applications of Reconfigurable Computing |
 | Session 25 - New Test Methods Targeting Non-Classical Faults |
A. Krstic, University of California, Santa Barbara
W.-C. Lai, University of California, Santa Barbara
L. Chen, University of California, San Diego
S. Dey, University of California, San Diego pp. 355
 | Session 26 - Special Session: How Do You Design a 10M Gate ASIC? |
 | Session 27 - Power Distribution Issues |
Dean Liu, Sun Microsystems Inc., Sunnyvale, CA pp. 391
Hui Zheng, Carnegie Mellon University, Pittsburgh, PA pp. 395
Hugo De Man, IMEC, Leuven, Belgium; ESAT - KU Leuven, Belgium pp. 399
 | Session 28 - Advances in Synthesis |
Christos P. Sotiriou, Institute of Computer Science (ICS), Foundation of Research and Technology - Hellas (FORTH), Greece pp. 415
 | Session 29 - Analog Synthesis & Design Methodology |
Hongzhou Liu, Carnegie Mellon University, Pittsburgh, Pennsylvania
Amit Singhee, Carnegie Mellon University, Pittsburgh, Pennsylvania pp. 437
E. Lauwers, Katholieke Universiteit Leuven, Heverlee, Belgium
M. Steyaert, Katholieke Universiteit Leuven, Heverlee, Belgium
G. Gielen, Katholieke Universiteit Leuven, Heverlee, Belgium pp. 449
 | Session 30 - Low-Power Physical Design |
Hai Li, Purdue University, West Lafayette, IN pp. 473
 | Session 31 - PANEL: Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible or Mission Irrelevant? |
 | Session 32 - Multi-Voltage, Multi-Threshold Design |
Yibin Ye, Circuit Research, Intel Labs, Hillsboro, OR
Liqiong Wei, Circuit Research, Intel Labs, Hillsboro, OR
Vivek De, Circuit Research, Intel Labs, Hillsboro, OR pp. 486
Dong-In Kang, University of Southern California/Information Sciences Institute, Arlington, VA
Jinwoo Suh, University of Southern California/Information Sciences Institute, Arlington, VA
Stephen P. Crago, University of Southern California/Information Sciences Institute, Arlington, VA pp. 492
 | Session 33 - Advanced Simulation Techniques |
 | Session 34 - Design Methodologies Meet Network Applications |
F. Catthoor, Katholieke Univ. Leuven; IMEC, Leuven, Belgium pp. 518
 | Session 35 - Advances in Analog Modeling |
 | Session 36 - Advances in Timing and Simulation |
Li-C. Wang, University of California, Santa Barbara pp. 566
 | Session 37 - PANEL: Formal Verification Methods: Getting around the Brick Wall |
 | Session 38 - Routing and Buffering |
Xiaoping Tang, University of Texas at Austin; Silicon Perspective, A Cadence Company, Santa Clara, CA pp. 584
 | Session 39 - System on Chip Design |
Dietmar M?, Chemnitz University of Technology, Germany pp. 602
R. Hermida, Universidad Complutense de Madrid, Spain pp. 612
 | Session 40 - Timing Analysis and Memory Optimization for Embedded Systems |
Thomas Erlebach, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Simon K?, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Lothar Thiele, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland pp. 616
Rolf Ernst, Technical University of Braunschweig, Germany pp. 622
M. Kandemir, Pennsylvania State University, University Park pp. 628
 | Session 41 - Processors and Acclerators for Embedded Applications |
 | Session 42 - PANEL: What's the Next EDA Driver? |
 | Session 43 - Cross-Talk Noise Analysis and Management |
Wayne Dai, University of California at Santa Cruz pp. 659
Lei He, University of Wisconsin, Madison pp. 669
 | Session 44 - Test Cost Reduction for SOCS |
 | Session 45 - Scheduling Techniques for Embedded Systems |
V. Delaluz, The Pennsylvania State University, University Park
M. Kandemir, The Pennsylvania State University, University Park
M. J. Irwin, The Pennsylvania State University, University Park pp. 697
I. Kadayif, Pennsylvania State University, University Park
M. Kandemir, Pennsylvania State University, University Park
U. Sezer, University of Wisconsin, Madison pp. 703
 | Session 46 - Special Session: Designing SoCs for Yield Improvement |
 | Session 47 - Advances in SAT |
 | Session 48 - Inductance and Substrate Analysis |
Tao Lin, Carnegie Mellon University, Pittsburgh, PA pp. 757
Adil Koukab, Swiss Federal Institute of Technology (EPFL), Switzerland pp. 767
E. Schrik, Delft University of Technology, The Netherlands pp. 771
 | Session 49 - Development of Processors and Communication Networks for Embedded Systems |
Y. Paviot, TIMA Laboratory, SLS Group, France
S. Yoo, TIMA Laboratory, SLS Group, France pp. 789
 | Session 50 - Moving Towards More Effective Validation |
Oded Lachish, IBM Research Laboratory in Haifa, Haifa University, Israel
Eitan Marcus, IBM Research Laboratory in Haifa, Haifa University, Israel
Shmuel Ur, IBM Research Laboratory in Haifa, Haifa University, Israel
Avi Ziv, IBM Research Laboratory in Haifa, Haifa University, Israel pp. 807
 | Session 51 - Special Session: Energy Efficient Mobile Computing |
 | Session 52 - Floorplanning and Placement |
Xiaoping Tang, University of Texas at Austin; Silicon Perspective, A Cadence Company, Santa Clara, CA pp. 848
Ke Zhong, Univ. of Illinois at Chicago, IL pp. 854
 | Session 53 - Circuit Effects in Static Timing |
 | Session 54 - Design Space Exploration for Embedded Systems |
Lothar Thiele, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Matthias Gries, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland
Simon K?, Swiss Federal Institute of Technology (ETH) Z?rich, Switzerland pp. 880
A. Bona, ALaRI, Lugano, Switzerland
M. Sami, Politecnico di Milano, Italy
C. Silvano, Universit? degli Studi di Milano, Italy
R. Zafalon, STMicroelectronics, Agrate B. (MI), Italy pp. 886
 | Session 55 - Behavioral Synthesis | Usage of this product signifies your acceptance of the Terms of Use.
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