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- DAC
- 2001
- 38th Conference on Design Automation (DAC'01)
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38th Conference on Design Automation (DAC'01) Las Vegas, Nevada, United States June 18-June 22 ISBN: 1-58113-297-2 Table of Contents
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| Session 1 - Panel: Teh Electronics Industry Supply Chain: Who Will Do What? |
| Session 2 - Nanometer Futures |
| Session 3 - System-Level Configurability: Bus, Interface, and Processor Design |
| Session 4 - Making Verification More Efficient |
Tony Ma, Advanced Technology, Synopsys Inc. pp. 35-40
Alferd K?lbl, Institute for EDA, technical University of Munich, Munich, Germany pp. 47-52
| Session 5 - SoC and High-Level DFT |
| Session 6 - Panel: The Next HDL: If C++ is the Answer, What was the Question? |
| Session 7 - Design for Subwavelength Manufacturability: Impact on EDA |
M. Thompson, Motorola DigitalDNA Laboratories, Austin, TX
R. Tian, Motorola DigitalDNA Laboratories, Austin, TX
E. Demircan, Motorola DigitalDNA Laboratories, Austin, TX
R. Wang, Motorola DigitalDNA Laboratories, Austin, TX
C. Yuan, Motorola DigitalDNA Laboratories, Austin, TX
W. Grobman, Motorola DigitalDNA Laboratories, Austin, TX pp. 73-78
Michel C?, Numerical Technologies, Inc., San Jose, CA pp. 93-96
| Session 8 - New Ideas in Logic Synthesis |
Kai Wang, University of California, Santa Barbara pp. 97-102
| Session 9 - Analog Design and Modeling |
A. Wagner, IBM Haifa Research Lab, MATAM, Israel pp. 127-132
| Session 10 - Scan-Based Testing |
| Session 11 - Panel: Your Core - My Problem? Integration and Verification of IP |
| Session 12 - Configurable Computing: Reconfiguring the Industry |
| Session 13 - Interconnnect Design Optimization |
Lei He, University of Wisconsin, Madison pp. 199-202
Jiping Liu, The University of Lethbridge, AB. Canada
Yu-Liang Wu, The Chinese University of HK, Shatin, Hong Kong pp. 203-208
| Session 14 - Power Estimation Techniques |
Amit Sinha, Massachusetts Institute of Technology, Cambridge pp. 220-225
| Session 15 - Functional Validation Based on Boolean Reasoning (BDD, SAT) |
| Session 16 - Verification: Life Beyond Algorithms |
| Session 17 - Dissecting an Embedded System: Lessons from Bluetooth |
| Session 18 - Algorithmic and Compiler Transformations for High-Level Synthesis |
| Session 19 - Gate Delay Calculation |
Geng Bai, University of Illinois, Urbana pp. 295-300
| Session 20 - Memory, Bus and Current Testing |
Cheng-Wen Wu, National Tsing Hua University, Hsinchu, Taiwan
Chi-Feng Wu, National Tsing Hua University, Hsinchu, Taiwan pp. 301-306
Majid Ahmadi, Ryerson Polytechnic University, Toronto, Canada pp. 313-316
Sujit Dey, University of California at San Diego, La Jolla, CA
Xiaoliang Bai, University of California at San Diego, La Jolla, CA
Li Chen, University of California at San Diego, La Jolla, CA pp. 317-320
| Session 21 - Panel: (When) Will FPGAs Kill ASIC's? |
| Session 22 - Inductance 101 and Beyond |
Tak Young, Monterey Design Systems, Sunnyvale, CA pp. 341-346
| Session 23 - Memory Optimization Techniques for DSP Processors |
A. Narayan, Louisiana State University, Baton Rouge, LA
Jinpyo Hong, Louisiana State University, Baton Rouge, LA pp. 359-364
Einar J. Aas, Norwegian University of Science and Technology, Trondheim, Norway pp. 365-370
| Session 24 - Technology Dependent Logic Synthesis |
Amit Singh, University of California, Santa Barbara pp. 383-388
Jason Cong, UCLA Computer Science Department, Los Angeles, CA pp. 389-394
| Session 25 - Collaborative and Distributed Design Frameworks |
Franc Brglez, Department of Computer Science, NC State University, Raleigh, NC pp. 401-406
T. Kuhn, University of Tuebingen, Germany pp. 413-418
| Session 26 - Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? |
| Session 27 - Closing the Gap Between ASIC and Custom: Design Examples |
| Session 28 - Energy and Flexibility Driven Scheduling |
| Session 29 - Representation and Optimization for Digital Arithmetic Circuits |
Zhan Yu, University of California, Los Angeles pp. 456-461
| Session 30 - Techniques for IP Protection |
Gang Qu, University of Maryland, College Park pp. 474-479
Gang Qu, University of Maryland, College Park pp. 490-493
| Session 31 - Visualization and Animation for VLSI Design |
Marc Najork, Compaq Systems Research Center, Palo Alto, CA pp. 506-511
| Session 32 - Application-Specific Customization for Systems-on-a-Chip |
| Session 33 - Satisfiability Solvers and Techniques |
| Session 34 - Power and Interconnect Analysis |
| Session 35 - Domain Specific Design Methodologies |
Kaijie Wu, Polytechnic University, Brooklyn, NY pp. 579-584
| Session 36 - Panel: Debate: Who has Nanometer Design Under Control? |
| Session 37 - Analysis and Implementation for Embedded Systems |
Amit Nandi, Carnegie Mellon University, Pittsburgh, PA pp. 599-604
| Session 38 - Industrial Case Studies in Verification |
Hyunglae Roh, Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
Yuntae Lee, Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
Hoon Choi, Samsung Electronics, Yongin-City, Kyunggi-Do, Korea pp. 611-616
| Session 39 - Integrated High-Level Synthesis Based Solutions |
Alex Doboli, State University of New York at Stony Brook pp. 629-634
| Session 40 - Timing Verification and Simulation |
Tong Xiao, Sun Microsystems, Inc., Palo Alto, CA pp. 653-656
| Session 41 - On-Chip Communication Architectures |
J. Rabaey, University of California at Berkeley
M. Sheets, University of California at Berkeley
A. Mihal, University of California at Berkeley
M. Sgroi, University of California at Berkeley pp. 667-672
Anh Nguyen, STMicroelectronics Inc., San Diego, CA pp. 678-683
| Session 42 - Compiler and Architecture Interactions |
J. Irwin, The Pennsylvania State University pp. 690-695
Olaf L?, Aachen University of Technology, Germany pp. 708-713
| Session 43 - Timing with Crosstalk |
Hai Zhou, Synopsys, Inc., Mountain View, CA pp. 714-719
Rafi Levy, Motorola Semiconductor Israel Ltd. Tel Aviv, Israel pp. 720-725
C. L. Liu, National Tsing Hua University, Taiwan
Ki-Wook Kim, Pluris, Incorporation, Cupertino, California pp. 732-737
| Session 44 - Low Power Design: Systems to Interconnect |
J? Henkel, C&C Research Laboratories, NEC USA, Princeton, NJ pp. 744-749
Sujit Dey, University of California, San Diego
Yi Zhao, University of California, San Diego pp. 754-757
Suhwan Kim, T. J. Watson Research Center, Yorktown Heights, NY pp. 758-763
| Session 45 - Floorplanning Representations and Placement Algorithms |
Jun Gu, Science & Technology University of Hong Kong
Yici Cai, Tsinghua University, Beijing, China
Yuchun Ma, Tsinghua University, Beijing, China pp. 770-775
| Session 46 - Panel: What Drives EDA Innovation? |
| Session 47 - Signal Integrity: Avoidance and Test Techniques |
| Session 48 - Novel Approaches to Microprocessor Design and Verification |
| Session 49 - Scheduling Techniques for Power Management |
Qing Wu, University of Southern California, Los Angeles
Qinru Qiu, University of Southern California, Los Angeles pp. 834-839
| Session 50 - Novel Devices and Yield Optimization |
Robert Schwencker, Technical University of Munich, Germany; Infineon Technologies AG, Munich, Germany
Stephen Zizala, Technical University of Munich, Germany; Infineon Technologies AG, Munich, Germany pp. 858-863 Usage of this product signifies your acceptance of the Terms of Use.
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