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Design Automation Conference (2001)
Las Vegas, Nevada, United States
June 18, 2001 to June 22, 2001
ISBN: 1-58113-297-2
TABLE OF CONTENTS
pp. viii
pp. xii
Reviewers (PDF)
pp. xv
pp. xix
Session 1 - Panel: Teh Electronics Industry Supply Chain: Who Will Do What?
Session 2 - Nanometer Futures
Himanshu Kaul , University of Michigan, Ann Arbor
Dennis Sylvester , University of Michigan, Ann Arbor
pp. 3-8
Wojciech Maly , Carnegie Mellon University, Pittsburgh, PA
pp. 9-14
Session 3 - System-Level Configurability: Bus, Interface, and Processor Design
Anand Raghunathan , UC San Diego, La Jolla, CA
Ganesh Lakshminarayana , NEC USA, Princeton, NJ
Kanishka Lahiri , NEC USA, Princeton, NJ
pp. 15-20
Darko Kirovski , Microsoft Research, Redmond, WA
Milenko Drinic , UCLA Computer Science Dep., Los Angeles, CA
pp. 27-30
Session 4 - Making Verification More Efficient
James Kukula , Advanced Technology, Synopsys Inc.
Pei-Hsin Jiang , Advanced Technology, Synopsys Inc.
Tony Ma , Advanced Technology, Synopsys Inc.
Yunshan Zhu , Advanced Technology, Synopsys Inc.
Dong Wang , Carnegie Mellon University
pp. 35-40
Saugata Chatterjee , University of Michigan
Todd Austin , University of Michigan
Fadi Aloul , University of Michigan
Karem Sakallah , University of Michigan
Maher Mneimneh , University of Michigan
pp. 41-46
Robert Damiano , Advanced Technology Group, Synopsys Inc.
James Kukula , Advanced Technology Group, Synopsys Inc.
pp. 47-52
Session 5 - SoC and High-Level DFT
Kwang-Ting Cheng , University of California, Santa Barbara, CA
Wei-Cheng Lai , University of California, Santa Barbara, CA
pp. 59-64
Chris Papachristou , Case Western Reserve University, Cleveland, OH
Kelly A. Ockunzzi , IBM Microelectronics, Burlington, VT
pp. 65-70
Session 6 - Panel: The Next HDL: If C++ is the Answer, What was the Question?
Session 7 - Design for Subwavelength Manufacturability: Impact on EDA
M. Thompson , Motorola DigitalDNA Laboratories, Austin, TX
R. Tian , Motorola DigitalDNA Laboratories, Austin, TX
E. Demircan , Motorola DigitalDNA Laboratories, Austin, TX
R. Wang , Motorola DigitalDNA Laboratories, Austin, TX
C. Yuan , Motorola DigitalDNA Laboratories, Austin, TX
W. Grobman , Motorola DigitalDNA Laboratories, Austin, TX
pp. 73-78
Jennifer Lund , IBM Research, Yorktown Hts., NY
Fook-Luen Heng , IBM Research, Yorktown Hts., NY
Lars Liebmann , IBM Microelectronics, East Fishkill, NY
pp. 79-84
Sridhar Panchapakesan , Avant! Corporation, Beaverton, OR
Jeffrey P. Mayhew , Avant! Corporation, Beaverton, OR
pp. 85-88
Luigi Capodieci , ASML MaskTools, Santa Clara, CA
Bob Socha , ASM Lithography, Santa Clara, CA
Olivier Toublan , Mentor Graphics, San Jose, CA
F. M. Schellenberg , Mentor Graphics, San Jose, CA
pp. 89-92
Michel C? , Numerical Technologies, Inc., San Jose, CA
Philippe Hurat , Numerical Technologies, Inc., San Jose, CA
Vinod Malhotra , Numerical Technologies, Inc., San Jose, CA
Michael Sanie , Numerical Technologies, Inc., San Jose, CA
pp. 93-96
Session 8 - New Ideas in Logic Synthesis
Kai Wang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Chih-Wei Chang , University of California, Santa Barbara
pp. 97-102
Bernd Steinbach , Freiberg Univ. of Mining and Techn., Germany
Alan Mishchenko , Portland State University, OR
pp. 103-108
Aviad Mintz , Bar-Ilan University, Israel
Udi Rotics , Netanya Academic College, Israel
Martin C. Golumbic , Bar-Ilan University, Israel
pp. 109-114
Valentina Ciriani , Dipartimento di Informatica, Pisa, Italy
pp. 115-120
Session 9 - Analog Design and Modeling
Behzad Razavi , University of California, Los Angeles, CA
pp. 121-126
Eliyahu Shamsaevc , IBM Haifa Research Lab, MATAM, Israel
David Goren , IBM Haifa Research Lab, MATAM, Israel
pp. 127-132
Ranga Vemuri , University of Cincinnati, OH
pp. 133-138
Georges Gielen , Katholieke Universiteit Leuven, Belgium
Wim Verhaegen , Katholieke Universiteit Leuven, Belgium
pp. 139-144
Session 10 - Scan-Based Testing
Irith Pomeranz , Purdue University, W. Lafayette, IN
pp. 145-150
Alex Orailoglu , University of California, San Diego, La Jolla, CA
Ismet Bayraktaroglu , University of California, San Diego, La Jolla, CA
pp. 151-155
Sudhakar Reddy , University of Iowa, IA
Irith Pomeranz , Purdue University, W. Lafayette, IN
pp. 156-161
Sheng-Nan Chiou , National Chung-Hsing University, Taiwan
Sying-Jyan Wang , National Chung-Hsing University, Taiwan
pp. 162-165
Krishnendu Chakrabarty , Duke University, Durham, NC
Anshuman Chandra , Duke University, Durham, NC
pp. 166-169
Session 11 - Panel: Your Core - My Problem? Integration and Verification of IP
Session 12 - Configurable Computing: Reconfiguring the Industry
Kurt Keutzer , UCLA Dept of EECS, Los Angeles, CA
Majid Sarrafzadeh , UCLA Dept of CS, Los Angeles, CA
Ingrid Verbauwhede , UCLA Dept of EE, Los Angeles, CA
pp. 172-177
Levent Caglar , Chameleon Systems, Inc., San Jose, CA
Bill Salefski , Chameleon Systems, Inc., San Jose, CA
pp. 178-183
Earl Killian , Tensilica, Inc., Santa Clara, CA
Chris Rowen , Tensilica, Inc., Santa Clara, CA
Dror Maydan , Tensilica, Inc., Santa Clara, CA
Albert Wang , Tensilica, Inc., Santa Clara, CA
pp. 184-188
Session 13 - Interconnnect Design Optimization
Paul Villarrubia , IBM Corporation, Austin, TX
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Jiang Hu , IBM Corporation, Austin, TX
pp. 189-194
Ryan Kastner , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
pp. 195-198
Lei He , University of Wisconsin, Madison
Irwan Luwandi , University of Wisconsin, Madison
Kevin M. Lepak , University of Wisconsin, Madison
pp. 199-202
Yu-Liang Wu , The Chinese University of HK, Shatin, Hong Kong
Jiping Liu , The University of Lethbridge, AB. Canada
Hongbing Fan , University of Victoria, BC. Canada
pp. 203-208
Session 14 - Power Estimation Techniques
N. Ranganathan , University of South Florida, Tampa, Florida
Sanjukta Bhanja , University of South Florida, Tampa, Florida
pp. 209-214
Ki-Seok Chung , Intel Corporation, Santa Clara, CA USA
Taewhan Kim , KAIST, Taejon, Korea
pp. 215-219
Anantha P. Chandrakasan , Massachusetts Institute of Technology, Cambridge
Amit Sinha , Massachusetts Institute of Technology, Cambridge
pp. 220-225
Session 15 - Functional Validation Based on Boolean Reasoning (BDD, SAT)
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Miroslav N. Velev , Carnegie Mellon University, Pittsburgh, PA
pp. 226-231
Malay K. Ganai , The University of Texas at Austin
Viresh Paruthi , IBM Enterprise Systems Group, Austin, TX
Andreas Kuehlmann , Cadence Berkeley Labs, Berkeley, CA
pp. 232-237
Bernd Becker , Albert-Ludwigs-University, Germany
Christoph Scholl , Albert-Ludwigs-University, Germany
pp. 238-243
Session 16 - Verification: Life Beyond Algorithms
Bob Bentley , Intel Corporation, Hillsboro, Oregon
pp. 244-248
Ken Albin , Motorola, Inc., Austin, TX
pp. 249-252
Duane Marhefka , The Ohio State University
Jennifer Stofer , IBM Corporation
Lyle Hanrahan , IBM Corporation
Joanne DeGroat , The Ohio State University
Fusun Ozguner , The Ohio State University
pp. 253-255
Session 17 - Dissecting an Embedded System: Lessons from Bluetooth
Barry Clark , Ericsson Technol, Licensing AB, Lund
Torbj? Grahm , Ericsson Technol, Licensing AB, Lund
pp. 256-231
Paul T. M. van Zeijl , Ericsson Eurolab Netherlands, The Netherlands
pp. 262
Session 18 - Algorithmic and Compiler Transformations for High-Level Synthesis
Nikil Dutt , University of California at Irvine
Rajesh Gupta , University of California at Irvine
Nick Savoiu , University of California at Irvine
Sunwoo Kim , University of California at Irvine
Alex Nicolau , University of California at Irvine
pp. 269-272
Giovanni De Micheli , Stanford University, CA
Armita Peymandoust , Stanford University, CA
pp. 277-282
Session 19 - Gate Delay Calculation
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Clayton B. McDonald , Carnegie Mellon University, Pittsburgh, PA
pp. 283-288
Sandeep K. Gupta , University of Southern California, Los Angeles, CA
Melvin A. Breuer , University of Southern California, Los Angeles, CA
pp. 289-294
Sudhakar Bobba , Sun Microsystems Inc., Palo Alto CA
Ibrahim N. Hajj , University of Illinois, Urbana
pp. 295-300
Session 20 - Memory, Bus and Current Testing
Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Chih-Wea Wang , National Tsing Hua University, Hsinchu, Taiwan
Kuo-Liang Cheng , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
Chi-Feng Wu , National Tsing Hua University, Hsinchu, Taiwan
pp. 301-306
Christos A. Papachristou , Case Western Reserve University, Cleveland, OH
Massood Tabib-Azar , Case Western Reserve University, Cleveland, OH
pp. 307-312
Xiaoliang Bai , University of California at San Diego, La Jolla, CA
Sujit Dey , University of California at San Diego, La Jolla, CA
pp. 317-320
Session 21 - Panel: (When) Will FPGAs Kill ASIC's?
Session 22 - Inductance 101 and Beyond
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 323-328
Min Zhao , Motorola Inc., Austin TX
Vladimir Zolotov , Motorola Inc., Austin TX
David Blaauw , Motorola Inc., Austin TX
Kaushik Gala , Motorola Inc., Austin TX
pp. 329-334
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 335-340
Mustafa Celik , Monterey Design Systems, Sunnyvale, CA
Tak Young , Monterey Design Systems, Sunnyvale, CA
Yi-Chang Lu , Stanford University, CA
pp. 341-346
Session 23 - Memory Optimization Techniques for DSP Processors
Catherine H. Gebotys , University of Waterloo, Ontario, Canada
pp. 347-352
Chaitali Chakrabarti , Arizona State University, Tempe, AZ
pp. 353-358
A. Narayan , Louisiana State University, Baton Rouge, LA
Jinpyo Hong , Louisiana State University, Baton Rouge, LA
J. Ramanujam , Louisiana State University, Baton Rouge, LA
pp. 359-364
Francky Catthoor , IMEC, Leuven, Belgium; EE.Dept. of Kath. Univ. Leuven
Einar J. Aas , Norwegian University of Science and Technology, Trondheim, Norway
pp. 365-370
Session 24 - Technology Dependent Logic Synthesis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 371-376
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Arindam Mukherjee , University of California, Santa Barbara
Amit Singh , University of California, Santa Barbara
pp. 383-388
Michail Romesis , UCLA Computer Science Department, Los Angeles, CA
pp. 389-394
Session 25 - Collaborative and Distributed Design Frameworks
Stephen W. Director , University of Michigan, Ann Arbor
Juan Antonio Carballo , IBM Austin Research Laboratory, TX
pp. 395-400
Hemang Lavana , Cisco Systems, Inc., Research Triangle Park, NC
Franc Brglez , Department of Computer Science, NC State University, Raleigh, NC
pp. 401-406
Milenko Drinic , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 407-412
M. Winterholer , University of Tuebingen, Germany
Marc Edwards , Cisco Systems, Inc., NC
T. Oppold , University of Tuebingen, Germany
Yaron Kashai , Verisity Design, Inc., Mountain View, CA
T. Kuhn , University of Tuebingen, Germany
pp. 413-418
Session 26 - Panel: When Will the Analog Design Flow Catch Up with Digital Methodology?
Session 27 - Closing the Gap Between ASIC and Custom: Design Examples
B. Nikolic , University of California at Berkeley
D. G. Chinnery , University of California at Berkeley
pp. 420-425
Pong-Fei Lu , IBM Research, Yorktown Heights, NY
pp. 426-431
Jim Schwartz , Intel Corporation, Hillsboro, OR
Matthew J. Parker , Intel Corporation, Hillsboro, OR
Stephen E. Rich , Intel Corporation, Hillsboro, OR
pp. 432-437
Session 28 - Energy and Flexibility Driven Scheduling
Seongsoo Lee , Ewha Woman's University
Jihong Kim , Seoul National University
pp. 438-443
Petru Eles , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
Traian Pop , Link?ping University, Sweden
Paul Pop , Link?ping University, Sweden
pp. 450-455
Session 29 - Representation and Optimization for Digital Arithmetic Circuits
Alan N. Willson , University of California, Los Angeles
Meng-Lin Yu , Agere Systems, Holmdel, NJ
pp. 456-461
Sanjeev Saluja , Cadence Design Systems, San Jose, CA
Anmol Mathur , Cadence Design Systems, San Jose, CA
pp. 462-467
Hyeong-Ju Kang , KAIST, Taejeon, Korea
In-Cheol Park , KAIST, Taejeon, Korea
pp. 468-473
Session 30 - Techniques for IP Protection
Gang Qu , University of Maryland, College Park
pp. 474-479
Jennifer L. Wong , University of California, Berkeley, California
Rupak Majumdar , University of California, Berkeley, California
pp. 480-485
Miodrag Potkonjak , University of California, Los Angeles
Jennifer L. Wong , University of California, Los Angeles
pp. 486-489
Hardware Metering (Abstract)
Gang Qu , University of Maryland, College Park
Farinaz Koushanfar , UC Berkeley, CA
pp. 490-493
Session 31 - Visualization and Animation for VLSI Design
Phillip J. Restle , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 494-499
Mark Horowitz , Stanford University, CA
pp. 500-505
Marc Najork , Compaq Systems Research Center, Palo Alto, CA
pp. 506-511
Session 32 - Application-Specific Customization for Systems-on-a-Chip
Sungjoo Yoo , SLS Group, TIMA Laboratory, France
Amer Baghdadi , SLS Group, TIMA Laboratory, France
Ahmed A. Jerraya , SLS Group, TIMA Laboratory, France
pp. 518-523
Luca Benini , DEIS, University of Bologna
Peter Glynn , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
Andrea Acquaviva , DEIS, University of Bologna
pp. 524-529
Session 33 - Satisfiability Solvers and Techniques
Ying Zhao , Princeton University
Sharad Malik , Princeton University
Matthew W. Moskewicz , UC Berkeley
pp. 530-535
Anubhav Gupta , Carnegie Mellon University, Pittsburgh, PA
Pranav Ashar , CCRL, NEC USA, Princeton, NJ
Aarti Gupta , CCRL, NEC USA, Princeton, NJ
pp. 536-541
Karem Sakallah , University of Michigan
Joonyoung Kim , Intel Corporation
pp. 542-545
Emil Gizdarski , University of Rousse, Bulgaria
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
pp. 546
Session 34 - Power and Interconnect Analysis
C.-J. Richard Shi , University of Washington, Seattle
pp. 550-554
Jason Cong , University of California, Los Angeles
pp. 555-558
Charlie Chung-Ping Chen , University of Wisconsin-Madison
Tsung-Hao Chen , University of Wisconsin-Madison
pp. 559-562
Jacob White , Massachusetts Institute of Technology
Luca Daniel , University of California, Berkeley
pp. 563-566
Lukas P. P. P. van Ginneken , Magma Design Automation Inc., Cupertino, CA
Massoud Pedram , Univ. of Southern California, Los Angeles
Amir H. Ajami , Univ. of Southern California, Los Angeles
pp. 567-572
Session 35 - Domain Specific Design Methodologies
Piyush Mishra , Polytechnic University, Brooklyn, NY
Yongkook Kim , IBM Corporation, Poughkeepsie, NY
Kaijie Wu , Polytechnic University, Brooklyn, NY
pp. 579-584
Advait Morge , University of California, Berkeley
Miodrag Potkonjak , University of California, Los Angeles
Farinaz Koushanfar , LSI Logic Corporation, Milpitas, California
Seapahn Meguerdichian , University of California, Los Angeles
pp. 585-590
Session 36 - Panel: Debate: Who has Nanometer Design Under Control?
Session 37 - Analysis and Implementation for Embedded Systems
F. Cucinotta , Politecnico di Torino, Italy
A. Serra , Politecnico di Torino, Italy
L. Lavagno , Universit? di Udine, Italy
pp. 593-598
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Amit Nandi , Carnegie Mellon University, Pittsburgh, PA
pp. 599-604
A. K. Raghunathan , NEC, C&C Research Labs, Princeton, NJ
G. Lakishminarayana , NEC, C&C Research Labs, Princeton, NJ
N. K. Jha , Princeton University, NJ
pp. 605-610
Session 38 - Industrial Case Studies in Verification
Hyunglae Roh , Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
Yuntae Lee , Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
Hoon Choi , Samsung Electronics, Yongin-City, Kyunggi-Do, Korea
pp. 611-616
Mike Benjamin , STMicroelectronics, UK
Daniel Geist , IBM Corp, MATAM, Haifa, Israel
Julia Dushina , STMicroelectronics, UK
pp. 617-622
Duaine Pryor , IKOS Systems Inc.
Charles Selvidge , IKOS Systems Inc.
Murali Kudlugi , IKOS Systems Inc.
pp. 623-628
Session 39 - Integrated High-Level Synthesis Based Solutions
Ranga Vemuri , University of Cincinnati, OH
Alex Doboli , State University of New York at Stony Brook
pp. 629-634
Alessandro Bogliolo , DEIS - University of Bologna, Italy
Luca Benini , DEIS - University of Bologna, Italy
Davide Bruni , DEIS - University of Bologna, Italy
pp. 641-646
Session 40 - Timing Verification and Simulation
Charles Selvidge , IKOS Systems Inc., Waltham, MA
Russell Tessier , University of Massachusetts, Amherst
pp. 647-652
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Tong Xiao , Sun Microsystems, Inc., Palo Alto, CA
pp. 653-656
Mohammad Mortazavi , Cadence Design Systems, San Jose, CA
Robert Palermo , Cadence Design Systems, San Jose, CA
John Hayes , University of Michigan, Ann Arbor
Karem Sakallah , University of Michigan, Ann Arbor
Hakan Yalcin , Cadence Design Systems, San Jose, CA
pp. 657-660
Kwang-Ting Cheng , University of California, Santa Barbara
Sandip Kundu , Intel Corporation, Austin
Jing-Jia Liou , University of California, Santa Barbara
pp. 661-666
Session 41 - On-Chip Communication Architectures
K. Keutzer , University of California at Berkeley
M. Sheets , University of California at Berkeley
S. Malik , Princeton University
A. Mihal , University of California at Berkeley
A. Sangiovanni-Vencentelli , University of California at Berkeley
M. Sgroi , University of California at Berkeley
pp. 667-672
Drew Wingard , Sonics, Inc., Mountain View, CA
pp. 673-677
Ramesh Rao , Univ. of CA, San Diego
Sujit Dey , Univ. of CA, San Diego
Anh Nguyen , STMicroelectronics Inc., San Diego, CA
Faraydon Karim , STMicroelectronics Inc., San Diego, CA
pp. 678-683
Brian Towles , Stanford University, CA
William J. Dally , Stanford University, CA
pp. 684-689
Session 42 - Compiler and Architecture Interactions
N. Vijaykrishnan , The Pennsylvania State University
I. Kadayif , The Pennsylvania State University
J. Irwin , The Pennsylvania State University
A. Parikh , The Pennsylvania State University
M. Kandemir , The Pennsylvania State University
pp. 690-695
Satish Pillai , The University of Texas at Austin, Austin
Gustavo de Veciana , The University of Texas at Austin, Austin
pp. 696-701
Margarida F. Jacome , The University of Texas at Austin
Gustavo A. de Veciana , The University of Texas at Austin
Viktor S. Lapinskii , The University of Texas at Austin
pp. 702-707
Martin Coors , Aachen University of Technology, Germany
Olaf L? , Aachen University of Technology, Germany
Heinrich Meyr , Aachen University of Technology, Germany
pp. 708-713
Session 43 - Timing with Crosstalk
Narendra Shenoy , Synopsys, Inc., Mountain View, CA
Hai Zhou , Synopsys, Inc., Mountain View, CA
pp. 714-719
Rafi Levy , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Vladimir Zolotov , Motorola Inc. Austin, TX
Chanhee Oh , Motorola Inc. Austin, TX
Jingyan Zuo , Motorola Inc. Austin, TX
Supamas Sirichotiyakul , Motorola Inc. Austin, TX
pp. 720-725
Ronald D. Blanton , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 726-731
Prashant Saxena , Intel Corporation, Hillsboro, Oregon
Seong-Ook Jung , University of Illinois at Urbana-Champaign
Sung-Mo Kang , University of California at Santa Cruz
C. L. Liu , National Tsing Hua University, Taiwan
Ki-Wook Kim , Pluris, Incorporation, Cupertino, California
pp. 732-737
Session 44 - Low Power Design: Systems to Interconnect
Anand Raghunathan , NEC, C&C Research Labs, Princeton, NJ
Niraj K. Jha , Princeton University, NJ
Ganesh Lakshminarayana , NEC, C&C Research Labs, Princeton, NJ
Weidong Wang , Princeton University, NJ
pp. 738-743
Haris Lekatsas , C&C Research Laboratories, NEC USA, Princeton, NJ
J? Henkel , C&C Research Laboratories, NEC USA, Princeton, NJ
pp. 744-749
Takayasu Sakurai , University of Tokyo, Japan
Youngsoo Shin , University of Tokyo, Japan
pp. 750-753
Yi Zhao , University of California, San Diego
Sujit Dey , University of California, San Diego
pp. 754-757
Marios C. Papaefthymiou , University of Michigan, Ann Arbor
Conrad H. Ziesler , University of Michigan, Ann Arbor
Suhwan Kim , T. J. Watson Research Center, Yorktown Heights, NY
pp. 758-763
Session 45 - Floorplanning Representations and Placement Algorithms
Yao-Wen Chang , National Chiao Tung University, Taiwan
Jai-Ming Lin , National Chiao Tung University, Taiwan
pp. 764-769
Xianlong Hong , Tsinghua University, Beijing, China
Yici Cai , Tsinghua University, Beijing, China
Sheqin Dong , Tsinghua University, Beijing, China
Chung-Kuan Cheng , University of California, San Diego
Yuchun Ma , Tsinghua University, Beijing, China
pp. 770-775
Patrick H. Madden , State University of New York at Binghamton
Mehmet Can Yildiz , State University of New York at Binghamton
pp. 776-779
C. Y. Roger Chen , Syracuse University, NY
Naresh Sehgal , EPD, Intel, Santa Clara, CA
pp. 780-783
M. Poncino , Politecnico di Torino, Italy
L. Macchiarulo , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
L. Benini , Universit? di Bologna, Italy
pp. 784-789
Session 46 - Panel: What Drives EDA Innovation?
Session 47 - Signal Integrity: Avoidance and Test Techniques
Amir Attarha , The University of Texas at Dallas
Mehrdad Nourani , The University of Texas at Dallas
pp. 792-797
Jamil Kawa , Synopsys Inc., Mountain View, CA
Don MacMillen , Synopsys Inc., Mountain View, CA
Jacob White , MIT, Cambridge, MA
pp. 804-809
Session 48 - Novel Approaches to Microprocessor Design and Verification
Wolfgang J. Paul , University of Saarland, Germany
pp. 810-815
Nobu Matsumoto , Toshiba Corporation Semiconductor Company, Japan
Kazuyoshi Kohno , Toshiba Corporation Semiconductor Company, Japan
pp. 816-821
Benjamin Tsien , Compaq Computer Corporation
Richard Lee , Compaq Computer Corporation
pp. 822-827
Session 49 - Scheduling Techniques for Power Management
Massoud Pedram , University of Southern California, Los Angeles
Qing Wu , University of Southern California, Los Angeles
Qinru Qiu , University of Southern California, Los Angeles
pp. 834-839
Pai H. Chou , University of California at Irvine
Fadi Kurdahi , University of California at Irvine
Jinfeng Liu , University of California at Irvine
pp. 840-845
Session 50 - Novel Devices and Yield Optimization
David B. Janes , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Rongtian Zhang , Purdue University, West Lafayette, IN
pp. 846-851
Hanseup Kim , University of Michigan, Ann Arbor
Alan J. Drake , University of Michigan, Ann Arbor
Gi-Joon Nam , University of Michigan, Ann Arbor
Seungbae Lee , University of Michigan, Ann Arbor
pp. 852-857
Helmut Graeb , Technical University of Munich, Germany
Michael Pronath , Technical University of Munich, Germany
Robert Schwencker , Technical University of Munich, Germany; Infineon Technologies AG, Munich, Germany
Stephen Zizala , Technical University of Munich, Germany; Infineon Technologies AG, Munich, Germany
Kurt Antreich , Technical University of Munich, Germany
pp. 858-863
Author Index (PDF)
pp. 865
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