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Design Automation Conference (2000)
Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
TABLE OF CONTENTS
pp. viii
pp. xii
Reviewers (PDF)
pp. xvi
pp. xxi
Session 1: Analog and RF
James R. Hellums , Mixed Signal Products, Texas Instruments Incorporated
L. Richard Carley , Carnegie Mellon University, Pittsburgh, Pennsylvania
Michael J. Krasnicki , Carnegie Mellon University, Pittsburgh, Pennsylvania
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, Pennsylvania
Rodney Phelps , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 1-6
M. Steyaert , Katholieke Universiteit Leuven, Belgium
C. De Ranter , Katholieke Universiteit Leuven, Belgium
G. Gielen , Katholieke Universiteit Leuven, Belgium
Peter Vancorenland , Katholieke Universiteit Leuven, Belgium
pp. 7-10
M. Steyaert , Katholieke Universiteit Leuven, Belgium
P. Vancorenland , Katholieke Universiteit Leuven, Belgium
B. De Muer , Katholieke Universiteit Leuven, Belgium
W. Sansen , Katholieke Universiteit Leuven, Belgium
G. Gielen , Flemish Fund for Scientific Research (FWO)
G. Van der Plas , Katholieke Universiteit Leuven, Belgium
C. De Ranter , Katholieke Universiteit Leuven, Belgium
pp. 11-14
Patrick McNamara , PDF Solutions Inc., San Jose, CA
Phillip Schumaker , PDF Solutions Inc., San Jose, CA
Sharad Saxena , PDF Solutions Inc., San Jose, CA
Dale Coder , PDF Solutions Inc., San Jose, CA
Carlo Gaurdiani , PDF Solutions Inc., San Jose, CA
pp. 15-18
C.-J. Richard Shi , University of Washington, Seattle, WA
Tao Pi , University of Washington, Seattle, WA
pp. 19-22
Session 2: BDD-Based Model Checking
James H. Kukula , Synopsys, Beaverton, OR
Kavita Ravi , Cadence, New Providence, NJ
Fabio Somenzi , University of Colorado, Boulder
In-Ho Moon , University of Colorado, Boulder
pp. 23-28
Kavita Ravi , Cadence Design Systems, New Providence, NJ
Fabio Somenzi , University of Colorado, Boulder
Roderick Bloem , University of Colorado, Boulder
pp. 29-34
Andreas Tiemeyer , Design Technology, Intel Corp.
Jin Yang , Intel Corp.
pp. 35-38
Bernd Becker , Albert-Ludwigs-University, Germany
Christoph Scholl , Albert-Ludwigs-University, Germany
Andreas Hett , Albert-Ludwigs-University, Germany
pp. 39-42
Session 3: Test Generation and Diagnosis
Masahiro Fujita , Fujitsu Laboratories of America, Sunnyvale, CA
Indradeep Ghosh , Fujitsu Laboratories of America, Sunnyvale, CA
pp. 43-48
Russell Tessier , University of Massachusetts, Amherst, MA
Ian G. Harris , University of Massachusetts, Amherst, MA
pp. 49-54
Alex Orailoglu , University of California, San Diego
Ismet Bayraktaroglu , University of California, San Diego
pp. 55-58
Sudhakar M. Reddy , University of Iowa, Iowa City
Irith Pomeranz , University of Iowa, Iowa City
pp. 59-62
Session 4: Interconnect Modeling
Junfeng Wang , Motorola Inc., Austin TX
Rajendran Panda , Motorola Inc., Austin TX
Vladimir Zolotov , Motorola Inc., Austin TX
Brian Young , Motorola Inc., Austin TX
David Blaauw , Motorola Inc., Austin TX
Kaushik Gala , Motorola Inc., Austin TX
pp. 63-68
John MacDonald , Mentor Graphics, OR
Lakshminarasimh Varadadesikan , Sun Microsystems, Palo Alto, CA
Wieze Xie , Hewlett-Packard, CA
Eileen You , Sun Microsystems, Palo Alto, CA
pp. 69-74
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
W. Scott , Synopsys, Mountain View, CA
D. MacMillen , Synopsys, Mountain View, CA
H. Levy , Synopsys, Mountain View, CA
pp. 75-78
Sudhakar Muddu , Silicon Graphics, Inc., Mountain View, CA
Egino Sarto , 3dfx Interactive, Inc., San Jose, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
pp. 79-84
Session 5: Special Session: Life at the End of CMOS Scaling (and Beyond)
Session 6: New Techniques for Synthesis and Mapping
Ralph Otten , Delft University of Technology, The Netherlands
Robert K. Brayton , University of California, Berkeley, USA
Yosinori Watanbe , Cadence Berkeley Labs, USA
Dirk-Jan Jongeneel , Delft University of Technology, The Netherlands
pp. 86-91
Maciej Ciesielski , University of Massachusetts, Amherst
Vigyan Singhal , Tempus Fugit, Inc., Albany, CA
Congguang Yang , University of Massachusetts, Amherst
pp. 92-97
Taewhan Kim , Korea Adv. Institute of Science & Technology, Taejon, Korea
C. L. Liu , National Tsing Hua Univ., Hsinchu, Taiwan
Junhyung Um , Korea Adv. Institute of Science & Technology, Taejon, Korea
pp. 98-103
D. F. Wong , University of Texas, Austin
Hai Zhou , Synopsys Inc., Mountain View, CA
pp. 104-107
Miodrag Potkonjak , University of California, Los Angeles
Seapahn Meguerdichian , University of California, Los Angeles
pp. 108-111
Session 7: Formal Verification
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Miroslav N. Velev , Carnegie Mellon University, Pittsburgh, PA
pp. 112-117
Kwang-Ting Cheng , University of California, Santa Barbara, CA
Chung-Yang Huang , University of California, Santa Barbara, CA
pp. 118-123
David L. Dill , Stanford University, CA
Chris Wilson , Stanford University, CA
pp. 124-129
Alan J. Hu , University of British Columbia, Vancouver
Sreeranga Rajan , Fujitsu Laboratories of America, Sunnyvale, CA
David W. Currie , Mentor Graphics, Billerica, MA
Masahiro Fujita , Fujitsu Laboratories of America, Sunnyvale, CA
pp. 130-135
Session 8: Test Issues for Deep-Submicron System-on-Chips
Erik Jan Marinissen , Philips Research Laboratories, The Netherlands
Yervant Zorian , LogicVision, Inc., San Jose, CA
pp. 136-141
Kaushik Roy , Purdue University, W. Lafayette, IN
Mike Rodgers , Intel Corp., Santa Clara, CA
Sujit Dey , Univ. of California, San Diego
Kwang-Ting Cheng , Univ. of California, Santa Barbara
pp. 142-149
Session 9: Clock and Power Grid Analysis for High Performance Designs
Rajat Chaudhry , Motorola Inc., Austin, TX
Rajendran V. Panda , Motorola Inc., Austin, TX
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Tim Edwards , Motorola Inc., Austin, TX
David Blaauw , Motorola Inc., Austin, TX
Min Zhao , Motorola Inc., Austin, TX
pp. 150-155
Joseph N. Kozhaya , University of Illinois, Urbana
Sani R. Nassif , IBM Austin Research Laboratory, Austin, TX
pp. 156-161
Rajendran Panda , Motorola Inc., Austin-TX
Tim Edwards , Motorola Inc., Austin-TX
David Blaauw , Motorola Inc., Austin-TX
Rajat Chaudhry , Motorola Inc., Austin-TX
pp. 162-167
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh, PA
Sani R. Nassif , IBM Austin Research Lab, Austin, TX
Ying Liu , Carnegie Mellon University, Pittsburgh, PA
pp. 168-171
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, MA
Rakesh Vallishayee , PDF Solutions, San Jose, CA
Sani Nassif , IBM, Austin, TX
Shiou Lin Sam , Massachusetts Institute of Technology, Cambridge, MA
Duane Boning , Massachusetts Institute of Technology, Cambridge, MA
Vikas Mehrotra , Massachusetts Institute of Technology, Cambridge, MA
pp. 172-175
Session 10: Panel: Design Closure: Hope or Hype?
Session 11: Algorithms for RF Simulation and Model Reduction
Joel Phillips , Cadence Design Systems, Inc., San Jose, CA
Baolin Yang , Cadence Design Systems, Inc., San Jose, CA
pp. 178-183
Joel R. Phillips , Cadence Berkeley Laboratories, San Jose, CA
pp. 184-189
Byron L. Krauter , IBM Corporation, Austin, TX
Chandramouli V. Kashyap , IBM Corporation, Austin, TX
pp. 190-195
Session 12: Verification and Debugging Methodologies
William R. Lee , System Level Design Methodology Leader, IBM, ASICs, NC
Amit Goel , Hamerschlag Hall, Pittsburgh, PA
pp. 196-200
Katherine R. Kohatsu , Intel Corporation, Hillsboro, Oregon
Robert B. Jones , Intel Corporation, Hillsboro, Oregon
Roope Kaivola , Intel Corporation, Hillsboro, Oregon
Carl-Johan H. Seger , Intel Corporation, Hillsboro, Oregon
Mark D. Aagaard , Intel Corporation, Hillsboro, Oregon
pp. 201-206
Miodrag Potkonjak , UCLA CS Department, Los Angeles, CA
William H. Mangione-Smith , UCLA EE Department, Los Angeles, CA
John Lach , UCLA EE Department, Los Angeles, CA
pp. 207-212
Session 13: Design Methods for Emerging Technologies
Kaustav Banerjee , Stanford University, CA
Amit Mehrotra , University of Illinois, Urbana-Champaign
Krishna C. Saraswat , Stanford University, CA
Shukri J. Souri , Stanford University, CA
pp. 213-220
S. Parameswaran , The University of Queensland, Australia
A. D. Rakic , The University of Queensland, Australia
V. E. Boros , The University of Queensland, Australia
pp. 221-226
Michael J. Kontz , University of Notre Dame, IN
Peter M. Kogge , University of Notre Dame, IN
Michael T. Niemier , University of Notre Dame, IN
pp. 227-232
Session 14: Signal Integrity
Amir Grinshpon , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Aurobindo Dasgupta , Motorola Inc., Austin, TX
Supamas Sirichotiyakul , Motorola Inc., Austin, TX
Vladimir Zolotov , Motorola Inc., Austin, TX
Boaz Orshav , Motorola Inc., Austin, TX
Chanlee Oh , Motorola Inc., Austin, TX
David Blaauw , Motorola Inc., Austin, TX
Gabi Braca , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Rafi Levy , Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
pp. 233-238
Dae-Jin Kim , Columbia University, New York, NY
Kenneth L. Shepard , Columbia University, New York, NY
pp. 239-242
Kaushik Roy , Purdue University, W. Lafayette, IN
Seung Hoon Choi , Purdue University, W. Lafayette, IN
Vivek De , Intel Corp. Hillsboro, OR
Yibin Ye , Intel Corp. Hillsboro, OR
Dinesh Somasekhar , Purdue University, W. Lafayette, IN
pp. 243-246
Tuyen V. Nguyen , IBM Austin Research Laboratory, Austin, TX
Janet M. Wang , University of California at Berkeley
pp. 247-252
Session 15: Panel: EDA Mees .COM: How E-Services Will Change the EDA Business Model
Session 16: Timing Analysis and Verification
Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Clayton B. McDonald , Carnegie Mellon University, Pittsburgh, PA
pp. 254-259
Soha Hassoun , Tufts University, Medford, MA
pp. 260-265
Karthik Rajagopal , Intel Corporation, Santa Clara, CA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Ravishankar Arunachalam , Carnegie Mellon University, Pittsburgh, PA
pp. 266-269
Abhijit Das , Motorola, Inc., Austin, TX
Rajendran Panda , Motorola, Inc., Austin, TX
David Blaauw , Motorola, Inc., Austin, TX
pp. 270-273
Session 17: Logic/Physical Co-Design
Sung Kyu Lim , UCLA Department of Computer Science, Los Angeles
Chang Wu , Aplus Design Technologies, Inc., Los Angeles, CA
Jason Cong , UCLA Department of Computer Science, Los Angeles
pp. 274-279
Sung-Mo Kang , University of Illinois at Urbana-Champaign, IL
Unni Narayanan , Intel Corporation, Santa Clara, CA
Ki-Wook Kim , University of Illinois at Urbana-Champaign, IL
pp. 280-285
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Peter Suaris , Mentor Graphics Corporation, Wilsonville, Oregon
Chung-Kuan Cheng , University of California, San Diego
Chih-Wei Chang , University of California, Santa Barbara
pp. 286-289
Hui Huang , Stanford University, CA
Jason Cong , University of California, Los Angeles
pp. 290-293
Session 18: Power Analysis and Optimization for Embedded Software
J? Henkal , NEC USA
Wayne Wolf , Princeton University
Haris Lekatsas , Princeton University
pp. 294-299
Alberto Macii , Politecnico di Torino, Italy
Massimo Poncino , Politecnico di Torino, Italy
Enrico Macii , Politecnico di Torino, Italy
Luca Benini , Universit? di Bologna, Italy
pp. 300-303
M. J. Irwin , The Pennsylvania State University, University Park
N. Vijaykrishnan , The Pennsylvania State University, University Park
W. Ye , The Pennsylvania State University, University Park
M. Kandemir , The Pennsylvania State University, University Park
pp. 304-307
R. Gebotys , Wilfrid Laurier University
S. Wiratunga , University of Waterloo, Canada
C. Gebotys , University of Waterloo, Canada
pp. 308-311
Anand Raghunathan , CCRL-NEC USA, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
Ganesh Lakshminarayana , CCRL-NEC USA, Princeton, NJ
Robert P. Dick , Princeton University, Princeton, NJ
pp. 312-315
Session 19: Embedded Compilation Techniques
Alex Nicolau , University of California, Irvine, CA
Nikil Dutt , University of California, Irvine, CA
Peter Grun , University of California, Irvine, CA
pp. 316-321
Stephen A. Edwards , Advanced Technology Group, Synopsys
pp. 322-327
Thierry Franzetti , IMEC-DESICS, Leuven, Belgium
Francky Catthoor , IMEC-DESICS, Leuven, Belgium
Thierry J.-F. Omn? , IMEC-DESICS, Leuven, Belgium
pp. 328-331
Jan Rabaey , University of California, Berkeley
Richard Newton , University of California, Berkeley
Naji Ghazal , University of California, Berkeley
pp. 332-335
Session 20: Panel: Future Systems-on-Chip: Software or Hardware Design?
Plenary Panel: Embedded Systems Design in the New Millenium
Session 21: New Techniques in Power Estimation and Performance Improvement
M. J. Irwin , The Pennsylvania State University, University Park
M. Kandemir , The Pennsylvania State University, University Park
N. Vijaykrishnan , The Pennsylvania State University, University Park
W. Ye , The Pennsylvania State University, University Park
pp. 340-345
W. Fornaciari , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
F. Salice , Politecnico di Milano, Italy
C. Brandolese , Politecnico di Milano, Italy
pp. 346-351
Massoud Pedram , University of Southern California, Los Angeles
Qing Wu , University of Southern California, Los Angeles
Qinru Qiu , University of Southern California, Los Angeles
pp. 352-356
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Luca Macchiarulo , University of California, Santa Barbara
pp. 357-360
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley, CA
Luca P. Carloni , University of California at Berkeley, CA
pp. 361-367
Session 22: Combined Global Routing, Buffering and Wiresizing
John Lillis , University of Illinois at Chicago
Sung-Woo Hur , University of Illinois at Chicago
Ashok Jagannathan , University of Illinois at Chicago
pp. 368-373
D. F. Wong , The University of Texas at Austin
Minghorng Lai , The University of Texas at Austin
pp. 374-378
Xin Yuan , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 379-384
Hiltrud Brocke , University of Hanover, Germany
Lars Hedrich , University of Hanover, Germany
Erich Barke , University of Hanover, Germany
Thorsten Adler , Infineon Technologies AG, Munich, Germany
pp. 385-389
Session 23: Advances in System Modeling and Synthesis
Simon N. Peffers , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
pp. 390-395
Hugo De Man , IMEC, Leuven, Belgium
D. Verkest , IMEC, Leuven, Belgium
Dirk Desmet , IMEC, Leuven, Belgium
pp. 396-401
J.-Y. Brunel , Philips Research, The Netherlands
K. A. Vissers , Philips Research, The Netherlands
P. Lieverse , Delft University of Technology, The Netherlands
P. van der Wolf , Philips Research, The Netherlands
W. M. Kruijtzer , Philips Research, The Netherlands
W. J. M. Smits , Philips Research, The Netherlands
G. Essink , Philips Research, The Netherlands
E. A. de Kock , Philips Research, The Netherlands
pp. 402-405
H. J. H. N. Kenter , Philips Research
L. Pasquier , Philips Research Laboratories Eindhoven, Paris
W. M. Kruijtzer , Philips Research
W. J. M. Smits , Philips Research
E. A. de Kock , Philips Research
F. P?trot , Universit? Pierre et Marie Curie, Paris
J.-Y. Brunel , Philips Research
pp. 406-409
Gaetano Borriello , University of Washington, Seattle
Pai H. Chou , University of California, Irvine
pp. 410-415
Larry Rudolph , Massachusetts Institute of Technology, Cambridge, MA
Prabhat Jain , Massachusetts Institute of Technology, Cambridge, MA
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge, MA
Derek Chiou , Massachusetts Institute of Technology, Cambridge, MA
pp. 416-419
Session 24: Designing Systems on a Chip
William R. Lee , IBM Microelectronics, Raleigh, NC
Reinaldo A. Bergamaschi , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 420-425
Pavlos Konas , Tensilica, Inc., Santa Clara, CA
G? Ezer , Tensilica, Inc., Santa Clara, CA
Marin? Puig-Medina , Tensilica, Inc., Santa Clara, CA
pp. 426-431
Session 25: Panel: The Future of System Design Languages
Session 26: Mixed Signal Design and Analysis
Ivo Bolsens , IMEC, Heverlee, Belgium
Marc Engels , IMEC, Heverlee, Belgium
Petr Dobrovoln? , IMEC, Heverlee, Belgium
Piet Wambacq , IMEC, Heverlee, Belgium
St?phane Donnay , IMEC, Heverlee, Belgium
Yves Rolain , Vrije Universiteit Brussel, Brussels, Belgium
Gerd Vandersteen , IMEC, Heverlee, Belgium
pp. 440-445
Ivo Bolsens , IMEC, Leuven, Belgium
Marc Engels , IMEC, Leuven, Belgium
Mustafa Badaroglu , IMEC, Leuven, Belgium
St?phane Donnay , IMEC, Leuven, Belgium
Marc van Heijningen , IMEC, Leuven, Belgium
pp. 446-451
J. Vandenbussche , Katholieke Universiteit Leuven
W. Daems , Katholieke Universiteit Leuven
W. Sansen , Katholieke Universiteit Leuven
G. Gielen , ESAT-MICAS
A. Van den Bosch , Katholieke Universiteit Leuven
G. Van der Plas , Katholieke Universiteit Leuven
pp. 452-457
Session 27: Floorplanning & Placement
Guang-Ming Wu , National Chiao Tung University, Hsinchu, Taiwan
Shu-Wei Wu , National Chiao Tung University, Hsinchu, Taiwan
Yao-Wen Chang , National Chiao Tung University, Hsinchu, Taiwan
Yun-Chih Chang , National Chiao Tung University, Hsinchu, Taiwan
pp. 458-463
Koen Lampaert , Conexant Systems Inc., Newport Beach, CA
Chung-Kuan Cheng , University of California, San Diego
Florin Balasa , University of Illinois, Chicago
Yingxin Pang , University of California, San Diego
pp. 464-467
Ernest S. Kuh , Univ. of California at Berkeley
Pinhong Chen , Univ. of California at Berkeley
pp. 468-471
Massoud Pedram , University of Southern California, Los Angeles
Shih-Lian Ou , University of Southern California, Los Angeles
pp. 472-476
Igor L. Markov , UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Andrew E. Caldwell , UCLA Computer Science Dept., Los Angeles, CA
pp. 477-482
Session 28: System Level Scheduling
A. Sangiovanni-Vincentelli , Univ. of California at Berkeley
F. Balarin , Cadence Berkeley Labs, Berkeley, CA
M. Di Natale , Universit? degli Studi di Pisa, Italy
pp. 483-488
Alberto Sangiovanni-Vincentelli , University of California Berkeley
Alex Kondratyev , Theseus Logic
Luciano Lavagno , Universit? di Udine
Marc Massot , Universitat de Girona
Sandra Moral , Universitat Polit?cnica de Catalunya
Yosinori Watanabe , Cadence Berkeley Labs
Claudio Passerone , Politecnico di Torino
Jordi Cortadella , Universitat Polit?cnica de Catalunya
pp. 489-494
Kiyoung Choi , Seoul National University, Korea
Daehong Kim , Seoul National University, Korea
Youngsoo Shin , University of Tokyo, Japan
pp. 495-500
Session 29: Architectures for Embedded Systems
Mani B. Srivastava , Dept. of Electrical Eng. at UCLA, Los Angeles, CA
Athanassios Boulis , Dept. of Electrical Eng. at UCLA, Los Angeles, CA
pp. 501-506
Jon Stockwood , Synopsys Inc., Mountain View, CA
Randolph Harr , Synopsys Inc., Mountain View, CA
Tim Callahan , Univ. of California, Berkeley, CA
Uday Kurkure , Synopsys Inc., Mountain View, CA
Ervan Darnell , Silicon Spice, Mountain View, CA
Yanbing Li , Synopsys Inc., Mountain View, CA
pp. 507-512
Anand Raghunathan , NEC USA, Princeton, NJ
Sujit Dey , University of California, San Diego, CA
Ganesh Lakshminarayana , NEC USA, Princeton, NJ
Kanishka Lahiri , University of California, San Diego, CA
pp. 513-518
Session 30: Panel: Embedded Systems Education
Session 31: Interconnect Analysis
Janet M. Wang , University of California at Berkeley
Ernest S. Kuh , University of California at Berkeley
Qingjian Yu , University of California at Berkeley
pp. 520-525
Anestis Dounavis , Carleton University, Ottawa, Canada
Michel Nakhla , Carleton University, Ottawa, Canada
Ramachandra Achar , Carleton University, Ottawa, Canada
Emad Gad , Carleton University, Ottawa, Canada
pp. 526-531
Session 32: High Level Synthesis for DSPs: Data Intensive Applications
Michael Kirkpatrick , University of Notre Dame, IN
Edwin Hsing-Mean Sha , University of Notre Dame, IN
Zhong Wang , University of Notre Dame, IN
pp. 540-545
J. Ramanujam , Louisiana State University, Baton Rouge, LA
M. Narasimhan , Intel Corporation, Dupont, WA
pp. 546-551
Heinrich Meyr , Integrated Signal Processing Systems, RWTH Aachen, Germany
Jens Horstmannshoff , Integrated Signal Processing Systems, RWTH Aachen, Germany
pp. 552-555
Ahmed Hemani , ESD, KTH, Sweden
Miguel Miranda , IMEC, Belgium
Francky Catthoor , IMEC, Belgium; Katholieke Universiteit Leuven
Peeter Ellervee , ESD, KTH, Sweden
pp. 556-559
Session 33: Embedded Tutorial: MOSFET Modeling and Circuit Design: Re-Establishing a Lost Connection
Session 34: Reconfigurable Computing Systems
Brent E. Nelson , Brigham Young University, Provo, UT
Brad L. Hutchings , Brigham Young University, Provo, UT
pp. 561-566
Yu-Tsang Chang , Chip Implementation Center, National Science Council of Taiwan, Taiwan
Yao-Wen Chang , National Chiao Tung University, Taiwan
pp. 567-572
Guangming Lu , University of California, Irvine
Ming-Hau Lee , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
Rafael Maestre , Universidad Complutense, Madrid, Spain
Eliseu Filho , COPPE/Federal University of Rio De Janeiro, Brazil
Fadi Kurdahi , University of California, Irvine
Hartej Singh , University of California, Irvine
pp. 573-578
Session 35: Panel: Survival Strategies for Mixed-Signal Systems-On-Chip
Session 36: Intellectual Property Protection & Re-Use
Jennifer Wong , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
David Liu , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 581-586
Miodrag Potkonjak , University of California, Los Angeles
Gang Qu , University of California, Los Angeles
pp. 587-592
Marcello Dalpasso , DEI - University of Padova, Italy
Alessandro Bogliolo , DI - University of Ferrara, Italy
Luca Benini , DEIS - University of Bologna, Italy
pp. 593-596
Franco Fummi , Universit? di Verona, Italy
Alessandro Fin , Universit? di Verona, Italy
pp. 597-600
Session 37: Correctness Issues in High Level Synthesis
Stefano Quer , Politecnico di Torino, Italy
Fabio Somenzi , University of Colorado, Boulder
Gianpiero Cabodi , Politecnico di Torino, Italy
pp. 601-606
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
Luciano Lavagno , Politecnico di Torino, Italy
Felice Balarin , Cadence Berkeley Laboratories, USA
Harry Hsieh , University of California at Berkeley
pp. 607-612
Joan Carletta , The Univ. of Akron, OH
Christos Papachristou , Case Western Reserve Univ., Cleveland, OH
Mehrdad Nourani , The Univ. of Texas at Dallas
pp. 613-618
Session 38: SOC Test Methodologies and Defect Modelling
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Sujit Dey , University of California, San Diego
Xiaoliang Bai , University of California, San Diego
pp. 619-624
Krishna Sekar , University of California at San Diego
Pablo Sanchez , University of Cantabria, Santander, Spain
Sujit Dey , University of California at San Diego
Ying Cheng , University of California at San Diego
Li Chen , University of California at San Diego
pp. 625-630
Mehradad Nourani , The Univ. of Texas at Dallas
Carco Lucas , The Univ. of Tehran, Iran
Amir Attarha , The Univ. of Texas at Dallas
pp. 631-636
Session 39: Embedded Tutorial: Bridging the Gap Between Full Custom and AISC Design
K. Keutzer , University of California at Berkeley
D. G. Chinnery , University of California at Berkeley
pp. 637-642
Andrew Chang , Stanford University, CA
Willaim J. Dally , Stanford University, CA
pp. 643-647
Session 40: Panel: Case Studies: Chip Design on the Bleeding Edge
Session 41: Layout Optimization
Keshab K. Parhi , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Vijay Sundararajan , University of Minnesota, Minneapolis
pp. 649-664
Kishore Kasamsetty , University of Minnesota, Minneapolis
Sachin Sapatnekar , University of Minnesota, Minneapolis
Mahesh Ketkar , University of Minnesota, Minneapolis
pp. 655-660
Vivek Tiwari , Intel Corporation, Santa Clara, CA
Mahadevamurty Nemani , Intel Corporation, Santa Clara, CA
pp. 661-666
Robert Boone , Motorola Inc., Austin, TX; University of Texas at Austin
D. F. Wong , University of Texas at Austin, TX
Ruiqi Tian , University of Texas at Austin, TX; Motorola Inc., Austin, TX
pp. 667-670
Alexander Zelikovsky , Georgia State University, Atlanta, GA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Gabriel Robins , University of Virginia, Charlottesville, VA
Yu Chen , UCLA Computer Science Dept., Los Angeles, CA
pp. 671-674
Session 42: Decision Procedures for cAD Problems
Karem A. Sakallah , University of Michigan, Ann Arbor, Michigan
Jo?o P. Marques-Silva , Technical University of Lisbon, IST/INESC, Lisbon, Portugal
pp. 675-680
I. Wegener , Universitaet Dortmund, Germany
K. Mohanram , University of Texas, Austin
Y. Lu , Carnegie Mellon University, Pittsburgh, PA
D. Moundanos , Fujitsu Labs of America, Sunnyvale, CA
J. Jain , Fujitsu Labs of America, Sunnyvale, CA
pp. 681-686
Jawahar Jain , Fujitsu Laboratories of America
Masahiro Fujita , Fujitsu Laboratories of America
Edmund Clarke , Carnegie Mellon University
Yuan Lu , Carnegie Mellon University
pp. 687-692
Session 43: New Frameworks for the EDA Field
Hua Lu , UC Berkeley EECS Dept., USA
Igor L. Markov , UCLA CS Dept., USA
Andrew B. Kahng , UCLA CS Dept., USA
Michael Oliver , UCLA CS Dept., USA
Yu Cao , UC Berkeley EECS Dept., USA
Dennis Sylvester , Synopsis, Inc., USA
Dirk Stroobandt , Ghent University ELIS Dept., Belgium
Farinaz Koushanfar , UCLA CS Dept., USA
Andrew E. Caldwell , UCLA CS Dept., USA
pp. 693-698
N. W. Schellingerhout , Philips Research Laboratories Eindhoven, The Netherlands
P. Bingley , Philips Research Laboratories Eindhoven, The Netherlands
W. P. M. van der Linden , Philips Research Laboratories Eindhoven, The Netherlands
P. van den Hamer , Philips Research Laboratories Eindhoven, The Netherlands
pp. 699-704
Andrew B. Kahng , OxSigen LLC, San Jose, California
Stefanus Mantik , OxSigen LLC, San Jose, California
Bart Thielges , UCLA Computer Science Dept., Los Angeles, CA
David George , UCLA Computer Science Dept., Los Angeles, CA
Stephen Fenstermaker , UCLA Computer Science Dept., Los Angeles, CA
pp. 705-710
Session 44: High Performance Microprocessor Design
J. Park , Samsung, Korea
J. Peter , IBM Austin Research Lab, Austin, TX
J. Silberman , IBM Watson Research Lab, Yorktown, NY
K. Lee , Sun Microsystems, CA
K. Nowka , IBM Austin Research Lab, Austin, TX
N. Aoki , IBM Austin Research Lab, Austin, TX
N. Kojima , IBM Austin Research Lab, Austin, TX
O. Kwon , IBM Austin Research Lab, Austin, TX
O. Takahashi , IBM Austin Research Lab, Austin, TX
P. Coulman , IBM Server Division, Austin, TX
P. Hofstee , IBM Austin Research Lab, Austin, TX
P. Villarrubia , IBM Server Division, Austin, TX
B. Flachs , Motorola, Austin, TX
S. Dhong , IBM Austin Research Lab, Austin, TX
D. Boerstler , IBM Austin Research Lab, Austin, TX
D. Meltzer , IBM Watson Research Lab, Yorktown, NY
S. Posluszny , IBM Austin Research Lab, Austin, TX
pp. 712-717
Qichao Richard Yin , Motorola Inc., Austin, TX
Jen-Tien Yen , Motorola Inc., Austin, TX
pp. 718-723
Irit Shitsevalov , IBM Haifa Research Laboratory, Israel
Ken Valk , IBM Rochester, MN
Kyle Nelson , IBM Rochester, MN
Russ Hoover , IBM Rochester, MN
Wayne Nation , IBM Rochester, MN
Cindy Eisner , IBM Haifa Research Laboratory, Israel
pp. 724-729
CGaAs PowerPC FXU (Abstract)
Keith L. Kraver , University of Michigan, Ann Arbor
P. Sean Stetson , University of Michigan, Ann Arbor
Phiroze N. Parakh , University of Michigan, Ann Arbor
Richard B. Brown , University of Michigan, Ann Arbor
Spencer M. Gold , University of Michigan, Ann Arbor
Todd D. Basso , University of Michigan, Ann Arbor
Claude R. Gauthier , University of Michigan, Ann Arbor
Alan J. Drake , University of Michigan, Ann Arbor
pp. 730-735
Session 45: Panel: When Bad Things Happen to Good Chips
Session 46: Large-Scale Parasitic Analysis
Jacob White , Massachusetts Institute of Technology, Cambridge
Joel Phillips , Cadence Berkeley Laboratories, San Jose, CA
Joe Kanapka , Massachusetts Institute of Technology, Cambridge
pp. 738-743
David E. Long , Lucent Technologies, Murray Hill, NJ
Sharad Kapur , Lucent Technologies, Murray Hill, NJ
pp. 744-749
Sung-Mo Kang , University of Illinois at Urbana-Champaign
Ching-Han Tsai , University of Illinois at Urbana-Champaign
pp. 750-755
Session 47: Advances in High Level Synthesis
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
William E. Dougherty , Carnegie Mellon University, Pittsburgh, PA
pp. 756-761
Alan N. Willson , University of California, Los Angeles
Kei-Yong Khoo , University of California, Los Angeles
Zhan Yu , University of California, Los Angeles
pp. 768-773
Session 48: Fault Simulation and Extraction of Low-Level Effects
Naim Ben Hamida , Fluence Technology Inc., Beaverton, OR
Bozena Kaminska , Fluence Technology Inc., Beaverton, OR
Khaled Saab , Fluence Technology Inc., Beaverton, OR
pp. 774-779
J. Casas , Intel Corporation, Hillsboro, OR
T. Tetzlaff , Intel Corporation, Hillsboro, OR
V. Krishnaswamy , Intel Corporation, Hillsboro, OR
pp. 780-785
R. D. Blanton , Carnegie Mellon University, Pittsburgh, PA
Kumar N. Dwarakanath , Carnegie Mellon University, Pittsburgh, PA
pp. 786-789
Sreejit Chakravarty , Intel Corporation, Santa Clara, CA
Carl D. Roth , Intel Corporation, Santa Clara, CA
Sujit T. Zachariah , Intel Corporation, Santa Clara, CA
pp. 790-793
Session 49: Low Power Design Techniques and Estimation
S. K. Nandy , Indian Institute of Science, Bangalore, India
M. Srikanth Rao , Indian Institute of Science, Bangalore, India
pp. 794-799
Jinsung Cho , Seoul National University, Korea
Kwanho Kim , Seoul National University, Korea
Naehyuck Chang , Seoul National University, Korea
pp. 800-805
Takayasu Sakurai , University of Tokyo, Japan
Seongsoo Lee , University of Tokyo, Japan
pp. 806-809
Kimiyoshi Usami , Toshiba Corporation, Kawasaki, Japan
Miodrag Potkonjak , University of California, Los Angeles
Naoyuki Kawabe , Toshiba Corporation, Kawasaki, Japan
Gang Qu , University of California, Los Angeles
pp. 810-813
Session 50: Panel: Emerging Companies-Acquiring Minds Want to Know
Author Index (PDF)
pp. 817
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