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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 794-799
S. K. Nandy , Indian Institute of Science, Bangalore, India
M. Srikanth Rao , Indian Institute of Science, Bangalore, India
ABSTRACT
In this paper we describe an area efficient power minimization scheme. "Control Generated Clocking" that saves significant amounts of power in datapath registers and clock drivers of sequential circuits. Power savings are achieved by making simple changes to the state machines controlling the datapath. These changes enable the control signals from the state machines themselves to be used as clocks for the datapath registers. Use of these control generated clocks makes the static timing analysis of designs implementing this scheme simpler when compared to techniques such as clock gating. This scheme preserves the cycle boundaries on which registers load data, thereby allowing reuse of functional test cases developed for the original circuit. In this paper we also describe timing requirements of a design in which this scheme has been implemented, cost-benefit aspects of this scheme and an algorithm for the automatic synthesis of control generated clocks. Results from application of this technique on a complex design are then discussed.
INDEX TERMS
fault modeling, fault simulation, hard faults, test vector generation
CITATION
S. K. Nandy, M. Srikanth Rao, "Power Minimization using Control Generated Clocks", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 794-799, doi:10.1109/DAC.2000.855422
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