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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 780-785
J. Casas , Intel Corporation, Hillsboro, OR
T. Tetzlaff , Intel Corporation, Hillsboro, OR
V. Krishnaswamy , Intel Corporation, Hillsboro, OR
ABSTRACT
This paper presents a fault simulation environment which accepts pure switch level or mixed switch/RT level descriptions of the design under test. Switch level fault injection strategies for the stuck-at, transition and logic bridge models are presented. A fault simulation algorithm is presented, along with design issues and optimizations. The fault simulation algorithm places no restrictions on the circuit styles used to implement designs. Mixed level simulation issues are discussed. Fault simulation performance numbers on large industrial benchmarks are reported.
INDEX TERMS
fault modeling, fault simulation, hard faults, test vector generation
CITATION
J. Casas, T. Tetzlaff, V. Krishnaswamy, "A Switch Level Fault Simulation Environment", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 780-785, doi:10.1109/DAC.2000.855419
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