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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 477-482
Igor L. Markov , UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Andrew E. Caldwell , UCLA Computer Science Dept., Los Angeles, CA
ABSTRACT
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the state-of-the-art after two decades of research in recursive bisection placement and implement a new placer, called Capo, to empirically study the achievable limits of the approach. From among recently proposed improvements to recursive bisection, Capo incorporates a leading-edge multilevel min-cut partitioner [7], techniques for partitioning with small tolerance [8], optimal min-cut partitioners and end-case min-wirelength placers [5], previously unpublished partitioning tolerance computations, and block splitting heuristics. On the other hand, our "good enough" implementation does not use "overlapping" [17], multi-way partitioners [17, 20], analytical placement, or congestion estimation [24, 35]. In order to run on recent industrial placement instances, Capo must take into account fixed macros, power stripes and rows with different allowed cell orientations. Capo reads industry-standard LEF/DEF, as well as formats of the GSRC bookshelf for VLSI CAD algorithms [6], to enable comparisons on available placement instances in the fixed-die regime. Capo clearly demonstrates that despite a potential mismatch of objectives, improved mincut bisection can still lead to improved placement wirelength and congestion. Our experiments on recent industrial benchmarks fail to give a clear answer to the question in the title of this paper. However, they validate a series of improvements to recursive bisection and point out a need for transparent congestion management techniques that do not worsen the wirelength of already routable placements. Our experimental flow, which validates fixed-die placement results by violation-free detailed auto-routability, provides a new norm for comparison of VLSI placement implementations.
INDEX TERMS
co-simulation, configurable processor cores, coverage analysis, design verification, system-on-chip, test generation
CITATION
Igor L. Markov, Andrew B. Kahng, Andrew E. Caldwell, "Can Recursive Bisection Alone Produce Routable Placements?", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 477-482, doi:10.1109/DAC.2000.855358
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