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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 458-463
Guang-Ming Wu , National Chiao Tung University, Hsinchu, Taiwan
Shu-Wei Wu , National Chiao Tung University, Hsinchu, Taiwan
Yao-Wen Chang , National Chiao Tung University, Hsinchu, Taiwan
Yun-Chih Chang , National Chiao Tung University, Hsinchu, Taiwan
ABSTRACT
We present in this paper an efficient, flexible, and effective data structure, B*-trees for non-slicing floorplans. B*-trees are based on ordered binary trees and the admissible placement presented in [1]. Inheriting from the nice properties of ordered binary trees, B*-trees are very easy for implementation and can perform the respective primitive tree, operations search, insertion, and deletion in only O(1), O(1), and O(n) times while existing representations for non-slicing floorplans need at least O(n) time for each of these operations, where n is the number of modules. The correspondence between an admissible placement and its induced B*-tree is 1-to-1 (i.e., no redundancy); further, the transformation between them takes only linear time. Unlike other representations for non-slicing floorplans that need to construct constraint graphs for cost evaluation, in particular, the evaluation can be performed on B*-trees and their corresponding placements directly and incrementally. We further show the flexibility of B*-trees by exploring how to handle rotated, pre-placed, soft, and rectilinear modules. Experimental results on MCNC benchmarks show that the B*-tree representation runs about 4.5 times faster, consumes about 60% less memory, and results in smaller silicon area than the O-tree one [1]. We also develop a B*-tree based simulated annealing scheme for floorplan design; the scheme achieves near optimum area utilization even for rectilinear modules.
INDEX TERMS
co-simulation, configurable processor cores, coverage analysis, design verification, system-on-chip, test generation
CITATION
Guang-Ming Wu, Shu-Wei Wu, Yao-Wen Chang, Yun-Chih Chang, "B*-Trees: A New Representation for Non-Slicing Floorplans", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 458-463, doi:10.1109/DAC.2000.855354
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