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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 379-384
Xin Yuan , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
ABSTRACT
Modern high performance design requires using a large number of buffers. In practice, buffers are organized into buffer blocks and planned in the early stages of design process [1]. Thus, the locations of buffer blocks are usually fixed prior to routing tree construction. In this paper we present the first algorithm for simultaneous routing tree construction and buffer insertion for multiple-pin nets under fixed buffer locations. Given a source and n sinks of a net, the required arrival time associated with each sink, and m buffers with fixed locations, our algorithm can construct a routing tree for this net with possible insertion of buffers at given locations such that the required arrival time at the source is maximized. Experimental results show that our algorithm is efficient to handle fixed buffer location constraints and can also be used for routing tree construction without buffer insertion. Moreover, it can handle obstacles and congestion which will benefit its adaption in a global router. Compared to the well-known BA-tree algorithm [2] followed by a post-processing step for handling fixed buffer location constraints, our algorithm outperforms it by up to 46% in terms of delay while using comparative wirelength.
INDEX TERMS
nanotechnology, quantum cellular automata
CITATION
Xin Yuan, Jason Cong, "Routing Tree Construction under Fixed Buffer Locations", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 379-384, doi:10.1109/DAC.2000.855340
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