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37th Conference on Design Automation (DAC'00)
Fast Post-Placement Rewiring using Easily Detectable Functional Symmetries
Los Angeles, CA
June 05-June 09
ISBN: 1-58113-1897-9
Malgorzata Marek-Sadowska, University of California, Santa Barbara
Peter Suaris, Mentor Graphics Corporation, Wilsonville, Oregon
Chung-Kuan Cheng, University of California, San Diego
Chih-Wei Chang, University of California, Santa Barbara
Timing convergence problem arises when the estimations made during logic synthesis can not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear time algorithm is proposed to detect functional symmetries in the Boolean network and is used as the basis for rewiring. Integration with an existing gate sizing algorithm further proves the effectiveness of our technique. Experimental results are very promising.
Index Terms:
nanotechnology, quantum cellular automata
Citation:
Malgorzata Marek-Sadowska, Peter Suaris, Chung-Kuan Cheng, Chih-Wei Chang, "Fast Post-Placement Rewiring using Easily Detectable Functional Symmetries," dac, pp.286-289, 37th Conference on Design Automation (DAC'00), 2000
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