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37th Conference on Design Automation (DAC'00)
Performance Driven Multi-Level and Multiway Partitioning with Retiming
Los Angeles, CA
June 05-June 09
ISBN: 1-58113-1897-9
Sung Kyu Lim, UCLA Department of Computer Science, Los Angeles
Chang Wu, Aplus Design Technologies, Inc., Los Angeles, CA
Jason Cong, UCLA Department of Computer Science, Los Angeles
In this paper, we study the performance driven multiw ay circuit partitioning problem with consideration of the significant difference of local and global interconnect delay induced by the partitioning. We develop an efficient algorithm HPM (Hierarchical Performance driven Multi-level partitioning) that simultaneously considers cutsize and delay minimization with retiming. HPM builds a multi-level cluster hierarchy and performs various refinement while gradually decomposing the clusters for simultaneous cutsize and delay minimization. We provide comprehensive experimental justification for each step involved in HPM and in-depth analysis of cutsize and delay tradeoff existing in the performance driven partitioning problem. HPM obtains (i) 7% to 23% better delay compared to the state-of-the-art cutsize driven hMetis [11] at the expense of 19% increase in cutsize, and (ii) 81% better cutsize compared to the state-of-the-art delay driven PRIME [2] at the expense of 6% increase in delay.
Index Terms:
nanotechnology, quantum cellular automata
Citation:
Sung Kyu Lim, Chang Wu, Jason Cong, "Performance Driven Multi-Level and Multiway Partitioning with Retiming," dac, pp.274-279, 37th Conference on Design Automation (DAC'00), 2000
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