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37th Conference on Design Automation (DAC'00)
ClariNet: A Noise Analysis Tool for Deep Submicron Design
Los Angeles, CA
June 05-June 09
ISBN: 1-58113-1897-9
Amir Grinshpon, Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Aurobindo Dasgupta, Motorola Inc., Austin, TX
Supamas Sirichotiyakul, Motorola Inc., Austin, TX
Vladimir Zolotov, Motorola Inc., Austin, TX
Boaz Orshav, Motorola Inc., Austin, TX
Chanlee Oh, Motorola Inc., Austin, TX
David Blaauw, Motorola Inc., Austin, TX
Gabi Braca, Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Rafi Levy, Motorola Semiconductor Israel Ltd. Tel Aviv, Israel
Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor designs. We present the overall approach and tool flow of ClariNet and discuss three critical large-processor design issues which have received limited discussion in the past. First, we present how the driver gates of a coupled interconnect network are represented with accurate linear models. Second, we show how to speed the analysis of large designs by using noise filters based on reduced interconnect representations and then pruning the nets coupled to a signal net. Third, we show how to incorporate logic and timing correlations into noise analysis to reduce its pessimism. We present the results from several industrial circuits, including a large high performance microprocessor design and a DSP design.
Index Terms:
nanotechnology, quantum cellular automata
Citation:
Amir Grinshpon, Aurobindo Dasgupta, Supamas Sirichotiyakul, Vladimir Zolotov, Boaz Orshav, Chanlee Oh, David Blaauw, Gabi Braca, Rafi Levy, "ClariNet: A Noise Analysis Tool for Deep Submicron Design," dac, pp.233-238, 37th Conference on Design Automation (DAC'00), 2000
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