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37th Conference on Design Automation (DAC'00)
High-Level Model of a WDMA Passive Optical Bus for a Reconfigurable Multiprocessor System
Los Angeles, CA
June 05-June 09
ISBN: 1-58113-1897-9
S. Parameswaran, The University of Queensland, Australia
A. D. Rakic, The University of Queensland, Australia
V. E. Boros, The University of Queensland, Australia
We describe the first iteration of a comprehensive model with which we can investigate the practical limits on optical bus bandwidth and number of bus processing modules for given signal power. The selection algorithm will ultimately allow programmable evaluation of system parameters bus bandwidth, optical power budget, electrical power budget, number of modules and space consumption for an optimal design that is suited to on-the-fly system reconfiguration.
Index Terms:
fault modeling, fault simulation, hard faults, test vector generation
Citation:
S. Parameswaran, A. D. Rakic, V. E. Boros, "High-Level Model of a WDMA Passive Optical Bus for a Reconfigurable Multiprocessor System," dac, pp.221-226, 37th Conference on Design Automation (DAC'00), 2000
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